VLSI课内实验——RTL级并行前缀加法器设计(8)

s(1) <= p(1) xor g(0); s(0) <= a(0) xor b(0) xor ci;

co <= (a(7) and b(7)) or (a(7) and c(7)) or (b(7) and c(7)); end process; end architecture;