VLSI课内实验——RTL级并行前缀加法器设计(5)

附：源代码

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity adder is

port(a :in std_logic_vector(7 downto 0); b :in std_logic_vector(7 downto 0); ci :in std_logic; clk:in std_logic;

s :out std_logic_vector(7 downto 0); co :out std_logic); end entity;

architecture behav of adder is

signal g:std_logic_vector(7 downto 0); signal p:std_logic_vector(7 downto 0); signal c:std_logic_vector(7 downto 0); begin process(clk) begin

g(7) <= a(7) and b(7);