VLSI课内实验——RTL级并行前缀加法器设计(6)

g(6) <= a(6) and b(6); p(6) <= a(6) xor b(6); g(5) <= a(5) and b(5); p(5) <= a(5) xor b(5); g(4) <= a(4) and b(4); p(4) <= a(4) xor b(4); g(3) <= a(3) and b(3); p(3) <= a(3) xor b(3); g(2) <= a(2) and b(2); p(2) <= a(2) xor b(2); g(1) <= a(1) and b(1); p(1) <= a(1) xor b(1); g(0) <= a(0) and b(0); p(0) <= a(0) xor b(0);

g(7) <= g(7) xor (p(7) and g(6)); p(7) <= p(7) and p(6);

g(5) <= g(5) xor (p(5) and g(4)); p(5) <= p(5) and p(4);

g(3) <= g(3) xor (p(3) and g(2)); p(3) <= p(3) and p(2);

g(1) <= g(1) xor (p(1) and g(0));