VLSI课内实验——RTL级并行前缀加法器设计(7)

g(7) <= g(7) xor (p(7) and g(5)); p(7) <= p(7) and p(5);

g(6) <= g(6) xor (p(6) and g(5)); p(6) <= p(6) and p(5);

g(3) <= g(3) xor (p(3) and g(1)); p(3) <= p(3) and p(1);

g(2) <= g(2) xor (p(2) and g(1)); p(2) <= p(2) and p(1);

g(7) <= g(7) xor (p(7) and g(3)); p(7) <= p(7) and p(3);

g(7) <= g(7) xor (p(7) and g(2)); p(7) <= p(7) and p(2);

g(7) <= g(7) xor (p(7) and g(1)); p(7) <= p(7) and p(1);

g(7) <= g(7) xor (p(7) and g(0)); p(7) <= p(7) and p(0); s(7) <= p(7) xor g(6); s(6) <= p(6) xor g(5); s(5) <= p(5) xor g(4); s(4) <= p(4) xor g(3); s(3) <= p(3) xor g(2);