山间雾野VLSI 设计的 FPGA 验证
else
count_4 <= count_4 + 1;
end if;
end if; end if; end process; qa<=count_4(0); qb<=count_4(1); qc<=count_4(2); qd<=count_4(3); END rtl;
② LED数码显示驱动模块的源代码： library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity display is
port( I0, I1, I2,I3 : in STD_LOGIC;
O_A, O_B, O_C, O_D, O_E, O_F, O_G : out STD_LOGIC);
end display;
architecture display of display is
signal M : STD_LOGIC_VECTOR(3 downto 0); signal O : STD_LOGIC_VECTOR(6 downto 0); begin
M <= I3&I2&I1&I0;
PROCESS(M) BEGIN
case M is
when "0000" => O <= "1000000"; --0 when "0001" => O <= "1111001"; --1 when "0010" => O <= "0100100"; --2
