VLSI 设计的 FPGA 验证(10)

VLSI 设计的 FPGA 验证

--content definition of component "debounce" library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --io signal declaraction entity debounce is

port(clk: in std_logic; --basic clock input

clr:in std_logic;

touch: in std_logic; --push button signal

push_out: out std_logic); --cleared push botton signal

end debounce;

architecture arch of debounce is

signal sample: std_logic;

--declaraction of self_built sampling pulse from clock begin

sampling_signal: block --input clk --output sample

signal delay:std_logic; --one_step delay

signal q: std_logic_vector(4 downto 0); --osc/2^5=32hz(31.25ms)

begin

process(clk) begin

if clr='1' then q<="00000"; delay<='0';

elsif rising_edge(clk) then

delay<=q(4); q<=q+1;