山间雾野VLSI 设计的 FPGA 验证
end if;
sample<=q(4) and not delay; --leading_edge differentiating
end process; end block sampling_signal; --cleared push botton signal generation cleared_push:block --input:clk,sample,touch --output:push_out
signal dff0,dff1:std_logic; --two_step delay ff signal push:std_logic; --output of rsff for push signal signal q1,q2:std_logic; begin
process(clk) begin
if clr='1' then
dff0<='0'; dff1<='0'; push<='0';
elsif rising_edge(clk) then
if sample='1' then dff1<=dff0;
dff0<=touch;
push<=dff0 and dff1; end if; end if; end process; process(clk) begin
if clr='1' then
q2<='0';
