听风细雨understanding of how HDL works can help you optimize your system. For example,
knowledge of the arbitration algorithm can help designers of multimaster systems
minimize the impact of arbitration on the system throughput.
Fundamentals of Implementation
System interconnect fabric for memory-mapped interfaces implements a partial
crossbar interconnect structure that provides concurrent paths between master and
slaves. System interconnect fabric consists of synchronous logic and routing resources
inside the FPGA.
For each component interface, system interconnect fabric manages Avalon-MM
transfers, interacting with signals on the connected component. Master and slave
interfaces can contain different signals and the system interconnect fabric handle any
adaptation necessary between them. In the path between master and slaves, the
system interconnect fabric might introduce registers for timing synchronization, finite
state machines for event sequencing, or nothing at all, depending on the services
required by the specific interfaces.
f For more information, refer to the Avalon Memory-Mapped Design Optimizations
chapter in the Embedded Design Handbook.
Functions of System Interconnect Fabric
System interconnect fabric logic provides the following functions:
■“Address Decoding” on page2–3
■“Datapath Multiplexing” on page2–4
■“Wait State Insertion” on page2–5
■“Pipelined Read Transfers” on page2–6
■“Arbitration for Multimaster Systems” on page2–9
■“Burst Adapters” on page2–14
■“Interrupts” on page2–15
■“Reset Distribution” on page2–16
The behavior of these functions in a specific SOPC Builder system depends on the
design of the components in the system and the settings made in SOPC Builder. The
remaining sections of this chapter describe how SOPC Builder implements each
function.
Address Decoding
Address decoding logic in the system interconnect fabric forwards appropriate
addresses to each slave. Address decoding logic simplifies component design in the
following ways:
December 2010Altera Corporation SOPC Builder User Guide
2–4Chapter 2:System Interconnect Fabric for Memory-Mapped Interfaces
Datapath Multiplexing
SOPC Builder User Guide December 2010Altera Corporation ■The system interconnect fabric selects a slave whenever it is being addressed by a
master. Slave components do not need to decode the address to determine when
they are selected.
■Slave addresses are properly aligned to the slave interface.
■
Changing the system memory map does not involve manually editing HDL. Figure 2–2 shows a block diagram of the address-decoding logic for one master and
two slaves. Separate address-decoding logic is generated for every master in a system.
As Figure 2–2 shows, the address decoding logic handles the difference between the
master address width ( and
It also maps only the necessary master address bits to access words in each slave’s
address space.
In SOPC Builder, the user-configurable aspects of address decoding logic are
controlled by the Base setting in the list of active components on the System Contents
tab, as shown in Figure 2–3.
Datapath Multiplexing
Datapath multiplexing logic in the system interconnect fabric drives the writedata
signal from the granted master to the selected slave, and the readdata signal from the
selected slave back to the requesting master.
Figure 2–2.Block Diagram of Address Decoding Logic
Figure 2–3.Base Settings in SOPC Builder Control Address Decoding
Chapter 2:System Interconnect Fabric for Memory-Mapped Interfaces2–5 Wait State Insertion
Figure2–4 shows a block diagram of the datapath multiplexing logic for one master
and two slaves. SOPC Builder generates separate datapath multiplexing logic for
every master in the system.
Figure2–4.Block Diagram of Datapath Multiplexing Logic
In SOPC Builder, the generation of datapath multiplexing logic is specified using the
connections panel on the System Contents tab.
Wait State Insertion
Wait states extend the duration of a transfer by one or more cycles. Wait state insertion
logic accommodates the timing needs of each slave, and causes the master to wait
until the slave can proceed. System interconnect fabric inserts wait states into a
transfer when the target slave cannot respond in a single clock cycle. System
interconnect fabric also inserts wait states in cases when slave read_enable and
write_enable signals have setup or hold time requirements.
Wait state insertion logic is a small finite-state machine that translates control signal
sequencing between the slave side and the master side. Figure2–5 shows a block
diagram of the wait state insertion logic between one master and one slave.
Figure2–5.Block Diagram of Wait State Insertion Logic
System interconnect fabric can force a master to wait for several reasons in addition to
the wait state needs of a slave. For example, arbitration logic in a multimaster system
can force a master to wait until it is granted access to a slave.
December 2010Altera Corporation SOPC Builder User Guide
