ug_sopc_builder-Altera FPGA嵌入式软核开发官方教程(4)

听风细雨 分享 2022-05-09 下载文档

■Take advantage of the one-hour online course, Using SOPC Builder.

■Download and run the checksum sample design described in Chapter9, SOPC

Builder Memory Subsystem Development Walkthrough.

You may have used SOPC Builder to create systems based on the Nios?II processor.

However, SOPC Builder is more than a Nios II system builder; it is a general-purpose

tool for creating systems that may or may not contain a processor and may include a

soft processor other than the Nios II processor.

SOPC Builder automates the task of integrating hardware components. Using

traditional design methods, you must manually write HDL modules to wire together

the pieces of the system. Using SOPC Builder, you specify the system components in a

GUI and SOPC Builder generates the interconnect logic automatically. SOPC Builder

generates HDL files that define all components of the system, and a top-level HDL file

that connects all the components together. SOPC Builder generates either Verilog

HDL or VHDL equally.

In addition to its role as a system generation tool, SOPC Builder provides features to

ease writing software and to accelerate system simulation. This chapter includes the

following sections:

■“Architecture of SOPC Builder Systems” on page1–1

■“Functions of SOPC Builder” on page1–5

■“Operating System Support” on page1–8

■“Talkback Support” on page1–8

Architecture of SOPC Builder Systems

An SOPC Builder component is a design module that SOPC Builder recognizes and

can automatically integrate into a system. You can also define and add custom

components or select from a list of provided components. SOPC Builder connects

multiple modules together to create a top-level HDL file called the SOPC Builder

system. SOPC Builder generates system interconnect fabric that contains logic to

manage the connectivity of all modules in the system.

December 2010Altera Corporation SOPC Builder User Guide

1–2Chapter 1:Introduction to SOPC Builder

Architecture of SOPC Builder Systems SOPC Builder Modules

1This document refers to components as the class definition for a module, for example a Nios?II processor. An instance is a parameterization of a component that's been added

to a system, for example cpu_0.

SOPC Builder modules are the building blocks for creating an SOPC Builder system.

SOPC Builder modules use Avalon? interfaces, such as memory-mapped, streaming,

and IRQ, for the physical connection of components. You can use SOPC Builder to

connect any logical device (either on-chip or off-chip) that has an Avalon interface.

There are different types of Avalon interfaces, as described in the Avalon Interface

Specifications.

f For details on the Avalon-MM interface refer to Chapter2, System Interconnect Fabric

for Memory-Mapped Interfaces. For details on the Avalon-ST interface, refer to

Chapter3, System Interconnect Fabric for Streaming Interfaces. For details about the

Avalon-ST interface protocol, refer to Avalon Interface Specifications.

SOPC Builder User Guide December 2010Altera Corporation

Chapter 1:Introduction to SOPC Builder1–3 Architecture of SOPC Builder Systems

Example System

Figure1–1 shows an FPGA design that includes an SOPC Builder system and custom

logic modules. You can integrate custom logic inside or outside the SOPC Builder

system. In this example, the custom component inside the SOPC Builder system

communicates with other modules through an Avalon-MM master interface. The

custom logic outside of the SOPC Builder system is connected to the SOPC Builder

system through a PIO interface. The SOPC Builder system includes two SOPC Builder

components with Avalon-ST source and sink interfaces. The system interconnect

fabric connects all of the SOPC Builder components using the Avalon-MM or

Avalon-ST system interconnect as appropriate.

Figure1–1.Example of an FPGA with a SOPC Builder System Generated by SOPC Builder

December 2010Altera Corporation SOPC Builder User Guide

1–4Chapter 1:Introduction to SOPC Builder

Architecture of SOPC Builder Systems

SOPC Builder User Guide December 2010Altera Corporation A component can be a logical device that is entirely contained within the SOPC

Builder system, such as the processor component shown in Figure 1–1. Alternately, a

component can act as an interface to an off-chip device, such as the DDR2 interface

component in Figure 1–1. In addition to the Avalon interface, a component can have

other signals that connect to logic outside the SOPC Builder system. Non-Avalon

signals can provide a special-purpose interface to the SOPC Builder system, such as

the PIO in Figure 1–1. These non-Avalon signals are described in Conduit Interface

chapter in the Avalon Interface Specifications .

Available Components

Altera and third-party developers provide ready-to-use SOPC Builder components,

including:

■

Microprocessors, such as the Nios II processor ■

Microcontroller peripherals, such as a Scatter-Gather DMA Controller and timer ■Serial communication interfaces, such as a UART and a serial peripheral interface

(SPI)

■General purpose I/O

■Communications peripherals, such as a 10/100/1000 Ethernet MAC

■

Interfaces to off-chip devices Custom Components

You can import HDL modules and entities that you write using Verilog HDL or

VHDL into SOPC builder as custom components. You use the following design flow

to integrate custom logic into an SOPC Builder system:

1.Determine the interfaces used to interact with your custom component.

2.Create the component logic using either Verilog HDL or VHDL.

b9e4216eaeaad1f346933fb2e the SOPC Builder component editor to create an SOPC Builder component

with your HDL files.

4.Instantiate your component in the system.

Once you have created an SOPC Builder component, you can use the component in

other SOPC Builder systems, and share the component with other design teams.

f For instructions on developin

g a custom SOPC Builder component, the details about

the file structure of a component, or the component editor, refer to Chapter 4, SOPC

Builder Components .

f For details on the Avalon-MM interface refer to Chapter 2, System Interconnect Fabric

for Memory-Mapped Interfaces . For details on the Avalon-ST interface, refer to

Chapter 3, System Interconnect Fabric for Streaming Interfaces .

Chapter 1:Introduction to SOPC Builder

1–5

Functions of SOPC Builder December 2010Altera Corporation SOPC Builder User Guide Third-Party Components

You can also use SOPC-ready components that were developed by third-parties.

Altera awards the SOPC Builder Ready certification to IP functions that are ready to integrate with the Nios II embedded processor or the system interconnect fabric via SOPC Builder. These cores support the Avalon-MM interface or the Avalon Streaming (Avalon-ST) interface and may include constraints, software drivers, simulation models, and reference designs when applicable.

To find SOPC Builder Ready third-party components that you can purchase and use in SOPC Builder systems, complete the following steps:

1.On the Tools menu in SOPC Builder, click Download Components .

2.On the Intellectual Property Solutions web page, type SOPC Builder ready r in

the box labeled Search for IP , Development Kits and Reference Designs .

Functions of SOPC Builder

This section describes the functions of SOPC Builder.

Defining and Generating the System Hardware

SOPC Builder allows you to design the structure of a hardware system. The GUI allows you to add components to a system, configure the components, and specify connectivity.

After you add and parameterize components, SOPC Builder generates the system interconnect fabric, and outputs HDL files to your project directory. During system generation, SOPC Builder creates the following items:

■An HDL file for the top-level SOPC Builder system and for each component in the

system. The top-level HDL file is named .v for Verilog HDL designs and .vhd for VHDL designs.

■Synopsis Design Constraints file (.sdc ) for timing analysis.

■ A Block Symbol File (.bsf ) representation of the top-level SOPC Builder system for use in Quartus II Block Diagram Files (.bdf ).

■An example of an instance of the top-level HDL file, .v or .vhd , which demonstrates how to instantiate the top-level HDL file in your code.

■ A data sheet called that provides a system overview

including the following information:

■

All external connections for the system ■ A memory map showing the address of each Avalon-MM slave with respect to

each Avalon-MM master to which it is connected

■

All parameter assignments for each component ■ A functional test bench for the SOPC Builder system and ModelSim ? simulation

project files

1–6Chapter 1:Introduction to SOPC Builder

SOPC Builder Design Flow

SOPC Builder User Guide December 2010Altera Corporation ■SOPC information file (.sopcinfo) that describes all of the components and

connections in your system. This file is a complete system description, and is used

by downstream tools such as the Nios II tool chain. It also describes the

parameterization of each component in the system; consequently, you can parse its

contents to get requirements when developing software drivers for SOPC Builder

components.

■ A Quartus II IP File (.qip ) that provides the Quartus II software with all required

ug_sopc_builder-Altera FPGA嵌入式软核开发官方教程(4).doc 将本文的Word文档下载到电脑

下一篇:STM8,STM32官方选型表(2014-08)

相关推荐
相关阅读
本类排行
× 游客快捷下载通道(下载后可以自由复制和排版)

下载本文档需要支付 7 元

支付方式:

开通VIP包月会员 特价:29元/月

注:下载文档有可能“只有目录或者内容不全”等情况,请下载之前注意辨别,如果您已付费且无法下载或内容有问题,请联系我们协助你处理。
微信:xxxxxx QQ:xxxxxx