远水孤云NAND01G-B2B, NAND02G-B2C Bus operations 17/624 Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus Operations , for a summary.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
4.1 Command Input
Command Input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 19 and T able 24 for details of the timings requirements.
4.2 Address Input
Address Input bus operations are used to input the memory addresses. Four bus cycles are
required to input the addresses for 1Gb devices whereas five bus cycles are required for the
2Gb device (refer to Table 6 and Table 7, Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 20 and T able 24 for details of the timings requirements.
4.3 Data Input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 21 and T able 24 and Table 25 for details of the timings requirements.
4.4 Data Output
Data Output bus operations are used to read: the data in the memory array, the Status
Register, the lock status, the Electronic Signature and the Unique Identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low. The data is output sequentially using the Read Enable
signal.
See Figure 22 and T able 25 for details of the timings requirements.
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Bus operations NAND01G-B2B, NAND02G-B2C
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4.5 Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up.
4.6 Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power consumption is reduced.
Table 5.
Bus Operations
Bus Operation E AL CL R W WP I/O0 - I/O7I/O8 - I/O15(1)
1.Only for x16 devices.
Command Input V IL V IL V IH V IH Rising X (2)2.WP must be V IH when issuing a program or erase command.
Command X Address Input V IL V IH V IL V IH Rising X Address X Data Input V IL V IL V IL V IH Rising V IH Data Input Data Input Data Output V IL V IL V IL Fallin g V IH X Data Output
Data Output
Write Protect X X X X X V IL X X Standby
V IH
X
X
X
X
V IL /V D
D
X
X
Table 6.
Address Insertion, x8 Devices
Bus Cycle (1)
1.Any additional address input cycles will be ignored.
I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O01st A7A6A5A4A3A2A1A02nd V IL V IL V IL V IL A11A10A9A83rd A19A18A17A16A15A14A13A124th A27A26A25A24A23A22A21A205th(2)
2.The fifth cycle is valid for 2Gb devices. A28 is for 2Gb devices only.
V IL
V IL
V IL
V IL
V IL
V IL
V IL
A28
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NAND01G-B2B, NAND02G-B2C
Bus operations
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Table 7.
Address Insertion, x16 Devices
Bus Cycle (1)
1.Any additional address input cycles will be ignored.
I/O8-I/O15I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O01st X A7A6A5A4A3A2A1A02nd X V IL V IL V IL V IL V IL A10A9A83rd X A18A17A16A15A14A13A12A114th X A26A25A24A23A22A21A20A195th(2)
2.The fifth cycle is valid for 2Gb devices. A27 is for 2Gb devices only.
X
V IL
V IL
V IL
V IL
V IL
V IL
V IL
A27
Table 8.
Address Definitions, x8
Address Definition A0 - A11Column Address A12 - A17Page Address
A18 - A27Block Address 1Gb device A18 - A28
Block Address
2Gb device
Table 9.
Address Definitions, x16
Address Definition A0 - A10Column Address A11 - A16Page Address
A17 - A26Block Address 1Gb device A17 - A27
Block Address
2Gb device
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5 Command Set
All bus write operations to the device are interpreted by the Command Interface. The
Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal is high. Device operations are selected by writing specific commands to the Command Register. The two-step command sequences for program and erase operations are imposed to maximize data security.The Commands are summarized in Table 10: Commands .
Table 10.
Commands
Command
Bus Write Operations (1)
1.The bus cycles are only shown for issuing the codes. The cycles required to input the
addresses or input/output data are not 8dc0c28c83d049649b6658dfmands accepted during
busy
1st CYCLE
2nd CYCLE 3rd CYCLE 4th CYCLE
Read
00h 30h ––Random Data Output 05h E0h ––Cache Read 00h 31h ––Exit Cache Read 34h –––Y es (2)
2.Only during Cache Read busy.
Page Program
(Sequential Input default)80h 10h ––Random Data Input 85h –––Copy Back Program 00h 35h 85h 10h Cache Program 80h 15h ––Block Erase 60h D0h ––Reset
FFh –––Y es Read Electronic Signature 90h –––Read Status Register
70h
–
–
–
Y es 元器件交易网8dc0c28c83d049649b6658df
NAND01G-B2B, NAND02G-B2C Device operations 21/626 Device operations
The following section gives the details of the device operations.
6.1 Read Memory Array
At Power-Up the device defaults to Read mode. To enter Read mode from another mode the
Read command must be issued, see Table 10: Commands .
Once a Read command is issued two types of operations are available: Random Read and
Page Read.
6.1.1 Random Read
Each time the Read command is issued the first read is Random Read.
6.1.2 Page Read
After the first Random Read access, the page data (2112 Bytes or 1056 Words) is
transferred to the Page Buffer in a time of t WHBH (refer to T able 25 for value). Once the
transfer is complete the Ready/Busy signal goes High. The data can then be read out
sequentially (from selected column address to last column address) by pulsing the Read
Enable signal.
The device can output random data in a page, instead of the consecutive sequential data, by
issuing a Random Data Output command .
The Random Data Output command can be used to skip some data during a sequential
data output.
The sequential operation can be resumed by changing the column address of the next data
to be output, to the address which follows the Random Data Output command.
The Random Data Output command can be issued as many times as required within a
page.
The Random Data Output command is not accepted during Cache Read operations.
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