远水孤云All devices have the Chip Enable Don’t Care feature, which allows code to be directly
downloaded by a microcontroller, as Chip Enable transitions during the latency time do not
stop the read operation.
All devices have the option of a Unique Identifier (serial number), which allows each device
to be uniquely identified.
The Unique Identifier options is subject to an NDA (Non Disclosure Agreement) and so not
described in the datasheet. For more details of this option contact your nearest ST Sales
office.
The devices are available in the following packages:
●TSOP48 (12 x 20mm)
●VFBGA63 (9.5 x 12 x 1mm, 0.8mm pitch) for NAND02G-B2C devices.
●VFBGA63 (9 x 11 x 1mm, 0.8mm pitch) for NAND01G-B2B devices.
In order to meet environmental requirements, ST offers the NAND01G-B2B and NAND02G-
B2C in ECOPACK? packages. ECOPACK packages are Lead-free. The category of second
Level Interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark.
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Description NAND01G-B2B, NAND02G-B2C
8/62For information on how to order these options refer to Table29: Ordering Information Scheme. Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to ’1’.
See Table2: Product Description, for all the devices available in the family.
Table 2.Product Description
Reference Part Number Density
Bus
Width
Page
Size
Block
Size
Memory
Array
Operatin
g Voltage
Timings
Package
Random
access
time
(max)
Sequential
access
time
(min)
Page
Program
time
(typ)
Block
Erase
(typ)
NAND01G
-B2B NAND01GR3B2B
1Gbit
x8
2048+
64
Bytes
128K+
4K
Bytes64
Pages x
1024
Blocks
1.7 to
1.95V
25μs50ns
200μs
2ms
VFBGA63
9x11mm NAND01GW3B2B
2.7 to
3.6V
25μs30ns TSOP48 NAND01GR4B2B
x16
1024+
32
Words
64K+
2K
Words
1.7 to
1.95V
25μs50ns(1) NAND01GW4B2B
2.7 to
3.6V
25μs30ns(1)
NAND02G
-B2C NAND02GR3B2C
2Gbit
x8
2048+
64
Bytes
128K+
4K
Bytes64
Pages x
2048
Blocks
1.7 to
1.95V
25μs50ns
2ms
VFBGA63
9.5x12mm NAND02GW3B2C
2.7 to
3.6V
25μs30ns TSOP48 NAND02GR4B2C
x16
1024+
32
Words
64K+
2K
Words
1.7 to
1.95V
25μs50ns(1) NAND02GW4B2C
2.7 to
3.6V
25μs30ns(1)
1.x16 organization only available for MCP 元器件交易网8dc0c28c83d049649b6658df
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NAND01G-B2B, NAND02G-B2C Description
1.x16 organization only available for MCP
9/62
Description NAND01G-B2B, NAND02G-B2C
10/62Table 3.Signal Names
I/O8-15Data Input/Outputs for x16 devices
I/O0-7
Data Input/Outputs, Address Inputs, or Command Inputs for x8 and
x16 devices
AL Address Latch Enable
CL Command Latch Enable
E Chip Enable
R Read Enable
RB Ready/Busy (open-drain output)
W Write Enable
WP Write Protect
V DD Supply Voltage
V SS Ground
NC Not Connected Internally
DU Do Not Use
元器件交易网8dc0c28c83d049649b6658df
元器件交易网8dc0c28c83d049649b6658df
NAND01G-B2B, NAND02G-B2C Description
1.Available only for NAND01GW3B2B and NAND02GW3B2C 8-bit devices.
11/62
元器件交易网8dc0c28c83d049649b6658df
Description NAND01G-B2B, NAND02G-B2C
1.Available only for NAND01GR3B2B and NAND02GR3B2C 8-bit devices.
12/62
NAND01G-B2B, NAND02G-B2C Memory array organization 13/622 Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series.
The memory array is organized in blocks where each block contains 64 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store Error correction Codes, software
flags or Bad Block identification.
In x8 devices the pages are split into a 2048 Byte main area and a spare area of 64 Bytes.
In the x16 devices the pages are split into a 1,024 Word main area and a 32 Word spare
area. Refer to Figure 5: Memory Array Organization .
2.1 Bad blocks
The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is
blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional
Bad Blocks may develop during the lifetime of the device.
The Bad Block Information is written prior to shipping (refer to Section 8.1: Bad Block
Management for more details).
Table 4: Valid Blocks shows the minimum number of valid blocks in each device. The values
shown include both the Bad Blocks that are present when the device is shipped and the Bad
Blocks that could develop later on.
These blocks need to be managed using Bad Blocks Management, Block Replacement or
Error Correction Codes (refer to Section 8: Software algorithms ).
Table 4.Valid Blocks
Density of Device
Min Max 2 Gbits
200820481 Gbit 10041024
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Memory array organization NAND01G-B2B, NAND02G-B2C
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NAND01G-B2B, NAND02G-B2C Signals description 15/623 Signals description
See Figure 2: Logic Diagram , and T able 3: Signal Names , for a brief overview of the signals
connected to this device.
3.1 Inputs/Outputs (I/O0-I/O7)
Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read
operation or input a command or data during a Write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2 Inputs/Outputs (I/O8-I/O15)
Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a Read operation or input data during a Write operation. Command and Address
Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3 Address Latch Enable (AL)
The Address Latch Enable activates the latching of the Address inputs in the Command
Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.
3.4 Command Latch Enable (CL)
The Command Latch Enable activates the latching of the Command inputs in the Command
Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
3.5 The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is low, V IL , the device is selected. If Chip Enable goes
high, v IH , while the device is busy, the device remains selected and does not go into standby
mode.
3.6 The Read Enable pin, R, controls the sequential data output during Read operations. Data
is valid t RLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
元器件交易网8dc0c28c83d049649b6658df
Signals description NAND01G-B2B, NAND02G-B2C 16/62 3.7 Data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10μs (min) is required before the
Command Interface is ready to accept a command. It is recommended to keep Write Enable high during the recovery time.
3.8 Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, V IL , the device does not accept any
program or erase operations.
It is recommended to keep the Write Protect pin Low, V IL , during power-up and power-down.
3.9 Ready/Busy (RB)
Controller is currently active. When Ready/Busy is Low, V OL , a read, program or erase
operation is in progress. When the operation completes Ready/Busy goes High, V OH .
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
Refer to the Section 11.1: Ready/Busy Signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.10 V DD Supply Voltage
V DD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever V DD is below V LKO (see
Table 22 and Table 23) to protect the device from any involuntary program/erase during
power-transitions.
Each device in a system should have V DD decoupled with a 0.1μF capacitor. The PCB track
widths should be sufficient to carry the required program and erase currents.
3.11 V SS Ground
Ground, V SS, is the reference for the power supply. It must be connected to the system
ground.
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