FPGA Quartus - II - 时钟约束 (4)

Example 6–17展示了用SDC命令来约束Figure 6–25中的I/O接口。 Example 6–17. SDC Commands to Constrain the I/O Interface # Create the base clock for the clock port

create_clock –period 10 –name clk_in [get_ports clk_in]

# Create a virtual clock with the same properties of the base clock driving # the source register

create_clock –period 10 –name virt_clk_in

# Create the input delay referencing the virtual clock and not the base # clock

# DO NOT use set_input_delay –clock clk_in # [get_ports data_in]

set_input_delay –clock virt_clk_in [get_ports data_in]