花骨朵儿IEEE 802.3 架构图解,包括10M,100M,1G,10G。
to-board and chip-to-optical module applications are not practical with this interface. Consequently, the XGMIIbus puts many limitations on the number of ports that may be implemented on a system line card.To overcome these issues, the 10 Gigabit Ethernet Task Force developed the XAUI interface. XAUI is a fullduplex interface that uses four (4) self-clocked serial differential links in each direction to achieve 10 Gb/s datathroughput. Each serial link operates at 3.125 Gb/s to accommodate both data and the overhead associatedwith 8B/10B coding. The self-clocked nature eliminates skew concerns between clock and data, and extends thefunctional reach of the XGMII by approximately another 50 cm. Conversion between the XGMII and XAUIinterfaces occurs at the XGXS (XAUI Extender Sublayer).XGMII和XAUI：在MAC和物理层之间是XGMII，XGMII为10吉比特全双工接口，其宽度为74bit，其中数据通道为64bit（单向数据通道为32bit），其余的为时钟和控制信号比特，它是连接以太网MAC层和物理层的桥梁。当XGMII提供10吉比特的数据通道时，由于时钟比特和数据比特再加上在时钟上升沿和下降沿锁存数据的定时要求，会导致路由选择的总线长度超出通常建议的7cm，因此使用XGMII总线会对系统线卡的端口数量产生很大限制，所以在芯片之间、各种板之间，以及芯片和光学组件之间的接口一般不选用此接口。为了克服这些困难，人们就提出了10吉比特连接单元接口（10Gigabit Attachment Unit Interface, XAUI）。XAUI是10吉比特以太网的重大变化之一，它能极大地改进和简化互连的路由选择。XAUI接口是一个全双工接口，它分别在两个方向上使用4对自同步串行链路来实现10Gbit/s的吞吐量。每一个串行链路使用8B/10B编码传送数据和开销，其工作速率为3.125Gbit/s，自同步特性消除了时钟和数据的相位偏移。XGMII和XAUI接口之间的转换由XAUI扩展子层（XAUI Extender Sublayer, XGXS）完成，在XAUI接口的信号源侧，某给定线上的数据和时钟字节在XGXS中被转变成8B/10B编码数据流。每对线上的数据流传输速率为3.125Gbit/s。在互连的信号宿侧，将时钟信号从到达的数据流中提取出来，再通过解码，重新映射成32bit XGMII格式。这样，74针的XGMII接口可以减少成8对即16针的XAUI接口；而且，XAUI的信源同步时钟方案允许XAUI交叉时钟域，从而在系统中除去复杂的定时校正。由于XAUI
接口结构紧凑，性能健壮，因此很适合用于芯片之间、各种板之间，以及芯片和光学组件之间。As seen in Figure 2, the XGMII interface is organized into 4 lanes of 8 bits. At the source side of the XAUIinterface bytes on a given lane as well as the timing clock are converted within the XGXS into an 8B / 10Bencoded data stream. Each data stream is transmitted across a single differential pair running at 3.125 Gb/s. Atthe destination side of the interconnect the clock is recovered from the incoming data stream, it is decoded andthen mapped back to the 32 bit XGMII format. . Thus, the 74 pin wide XGMII interface is reduced to a XAUIinterface consisting of 8 differential pair or 16 pins. Furthermore, the source synchronous clocking schemeallows XAUI to cross clock domains, which eliminates elaborate timing correction within the system.XAUI – A Self-Managed InterfaceThe XAUI employs the same robust 8B/10B transmission code as 1000BASE-X. With 8b/10b coding, there aremore than enough code possibilities for mapping an 8-bit word. Some of the extra code groups are used forcontrol signaling; such as start of frame, end of frame, channel idle, link configurations and so on. Control wordsare used during the Inter-Packet Gap (IPG) time and during idle periods to continuously allow the interface tomaintain word and lane allignment. This is done with no upper layer support requirement, and allows XAUI tofunction as a self-managed interface.Frame synchronization and lane alignment is essentially a two-step process. Code group synchronization isachieved on each lane upon reception of three ordered sets for the lane. One easily recognizable patterns
