搞怪之王
第 44 页
else
if f=\
data6<=2*d5+c5;data7<=2*b5+a5;
else
if(data5>10) then
data6<=1;data7<=data5-10;
else
data6<=0;data7<=data5;
end if;
end if;
end if;
else
data6<=12;data7<=12;
end if;
end process; process(f) begin
case f is
when \when \when \when others=>data8<=12;
end case;
end process; process(clk,rst) begin
if(rst='0')then
cnt_scan<=\
elsif(clk'event and clk='1')then
第 45 页
cnt_scan<=cnt_scan+1;
end if; end process; process(cnt_scan) begin
case cnt_scan is
when\when\when\when others=>null;
end case;
end process; process(en_xhdl) begin
case en_xhdl is
when \when \when \when others => null;
end case;
end process; process(data4) begin
case data4 is
when 0 =>
dataout_xhdl1 <= \ when 1 =>
dataout_xhdl1 <= \ when 2 =>
第 46 页
dataout_xhdl1 <= \ when 3 =>
dataout_xhdl1 <= \ when 4 =>
dataout_xhdl1 <= \ when 5 =>
dataout_xhdl1 <= \ when 6 =>
dataout_xhdl1 <= \ when 7 =>
dataout_xhdl1 <= \ when 8 =>
dataout_xhdl1 <= \ when 9 =>
dataout_xhdl1 <= \ when 10 =>
dataout_xhdl1 <= \ when 11 =>
dataout_xhdl1 <= \ when 12 =>
dataout_xhdl1 <= \ when others=>null;
end case;
end process; end arch;
第 47 页
附录A8 mux51模块的实现程序
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mux51 is port(
a,b,c,d,e:in std_logic; y1,y2,y3,y4,y5:in std_logic; y:out std_logic;
f1,f2,f3,f4,f5:out std_logic );
end mux51;
architecture rtl of mux51 is
signal m:std_logic_vector(4 downto 0); begin
m<=a&b&c&d&e; process(m) begin
case m is
when \when \when \when \when \when others=>f1<='0';f2<='0';f3<='0';f4<='0';f5<='0';y<='0'; end case;
end process; end rtl;
第 48 页
附录B顶层文件设计原理图
图B1 顶层文件设计原理图
