夏末的晨曦Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particula
ParetoPointsinSRAMDesignUsingtheSleepyStackApproach
JunCheolParkandVincentJ.MooneyIIISchoolofElectricalandComputerEngineeringGeorgiaInstituteofTechnology,Atlanta,GA30332
{jcpark,mooney}@ece.gatech.eduAbstract
LeakagepowerconsumptionofcurrentCMOStech-nologyisalreadyagreatchallenge.ITRSprojectsthatleakagepowerconsumptionmaycometodominateto-talchippowerconsumptionasthetechnologyfeaturesizeshrinks.LeakageisaseriousproblemparticularlyforSRAMwhichoccupieslargetransistorcountinmoststate-of-the-artchipdesigns.Weproposeanovelultra-lowleakageSRAMdesignwhichwecall“sleepystackSRAM.”Unlikemanyotherpreviousapproaches,sleepystackSRAMcanretainlogicstateduringsleepmode,http://www.77cn.com.cnparedtothebestalternativewecould nd,a6-TSRAMcellwithhigh-Vthtransistors,thesleepystackSRAMcellwith2xVthat110oCachievesmorethan2.77Xleakagepowerreduc-tionatacostof16%delayincreaseand113%areain-crease.Alternatively,bywideningwordlinetransistorsandtransistorsinthepull-downnetwork,thesleepystackSRAMcellcanachieves2.26Xleakagereductionwithoutincreasingdelayatacostofa125%areapenalty.
1Introduction
PowerconsumptionisoneofthetopconcernsofVeryLargeScaleIntegration(VLSI)circuitdesign,forwhichComplementaryMetalOxideSemiconductor(CMOS)istheprimarytechnology.Today’sfocusonlowpowerisnotonlybecauseoftherecentgrowingdemandsofmobileapplications.Evenbeforethemobileera,powerconsump-tionhasbeenafundamentalproblem.PowerconsumptionofCMOSconsistsofdynamicandstaticcomponents.Al-thoughdynamicpoweraccountedfor90%ormoreofthetotalchippowerpreviously,asthefeaturesizeshrinks,e.g.,to0.09µand0.065µ,staticpowerhasbecomeagreatchallengeforcurrentandfuturetechnologies.BasedontheInternationalTechnologyRoadmapforSemiconduc-tors(ITRS)[1],Kimetal.reportthatsubthresholdleakagepowerdissipationofachipmayexceeddynamicpowerdissipationatthe65nmfeaturesize[2].
Oneofthemainreasonscausingtheleakagepowerin-creaseisincreaseofsubthresholdleakagepower.Whentechnologyfeaturesizescalesdown,supplyvoltageandthresholdvoltagealsoscaledown.Subthresholdleakagepowerincreasesexponentiallyasthresholdvoltagede-creases.Furthermore,thestructureoftheshortchanneldevicelowersthethresholdvoltageevenlower.Anothercontributortoleakagepowerisgate-oxideleakagepower
duetothetunnelingcurrentthroughthegate-oxideinsu-lator.Althoughgate-oxideleakagepowermaybecom-parabletosubthresholdleakagepowerinnanoscaletech-nology,weassumeothertechniqueswilladdressgate-oxideleakage;forexample,high-kdielectricgateinsu-latorsmayprovideasolutiontoreducegate-leakage[2].Therefore,thispaperfocusesonreducingsubthresholdleakagepowerconsumption.
AlthoughleakagepowerconsumptionisaproblemforallCMOScircuits,inthispaperwefocusonSRAMbe-causeSRAMtypicallyoccupieslargeareaandtransistorcountinaSystem-on-a-Chip(SoC).Furthermore,consid-eringanembeddedprocessorexample,SRAMaccountsfor60%ofareaand90%ofthetransistorcountinIntelXScale[3],andthusmaypotentiallyconsumelargeleak-agepower.
Inthispaper,weproposethesleepystackSRAMcelldesign,whichisamixtureofchangingthecircuitstructureaswellasusinghigh-Vth.Thesleepystacktechnique[4]achievesgreatlyreducedleakagepowerwhilemaintainingpreciselogicstateinsleepmode,whichmaybecrucialforaproductspendingthemajorityofitstimeinsleeporstand-bymode.Basedonthesleepystacktechnique,thesleepystackSRAMcelldesigntakesadvantageofultra-lowleakageandstatesaving.
Thispaperisorganizedasfollows.InSection2,priorworkinlow-leakageSRAMdesignisdiscussed.InSec-tion3,oursleepystackSRAMcelldesignapproachisproposed.InSection4and5,experimentalmethodologyandtheresultsarepresented.InSection6,conclusionsaregiven.
2Previouswork
Inthissection,wediscussstate-of-the-artlow-powermemorytechniques,especiallySRAMandcachetech-niquesonwhichourresearchfocuses.
Oneeasywaytoreduceleakagepowerconsumptionisbyadoptinghigh-VthtransistorsforallSRAMcelltran-sistors.Thissolutionissimplebutincursdelayincrease.Azizietal.observethatinnormalprograms,mostofthebitsinacachearezeros.Therefore,Azizietal.pro-poseanAsymmetric-CellCache(ACC),whichpartiallyapplieshigh-VthtransistorsinanSRAMcelltosaveleak-agepoweriftheSRAMcellisinthezerostate[5].How-ever,theACCleakagepowersavingsarequitelimitedincaseofabenchmarkwhich llsSRAMwithmostlynon-
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particula
zerovalues.Niietal.proposeAuto-Backgate-ControlledMulti-ThresholdCMOS(ABC-MTCMOS),whichusesReverse-BodyBias(RBB)toreduceleakagepowercon-sumption[6].RBBincreasesthresholdvoltagewithoutlosinglogicstate.Thisincreasedthresholdvoltagere-ducesleakagepowerconsumptionduringsleepmode.However,sincetheABC-MTCMOStechniqueneedstochargelargewells,ABC-MTCMOSrequiressigni canttransitiontimeandpowerconsumption.
Theforcedstacktechniqueachievesleakagepowerre-ductionbyforcingastackstructure[7].Thistechniquebreaksdownexistingtransistorsintotwotransistorsandtakesanadvantageofthestackeffect,whichreducesleak-agepowerconsumptionbyconnectingtwoormoreturnedofftransistorsserially.Theforcedstacktechniquecanbeappliedtoamemoryelementsuchasaregister[8]oranSRAMcell[9].However,delayincreasemayoccurduetoincreasedresistance,andthelargestleakagesavingsre-portedunderspeci cconditionsis90%comparedtocon-ventionalSRAMin0.07µtechnology[9].
http://www.77cn.com.cningsleeptransistors,thegated-VddSRAMcellblockspull-upnetworksfromtheVddrail(pMOSgated-Vdd)and/orblockspull-downnetworksfromtheGndrail(nMOSgated-Vdd)[10].Thegated-VddSRAMcellachieveslowleakagepowerconsumptionfromboththestackeffectandhigh-Vthsleeptransistors.However,thegated-VddSRAMcell[10]losesstatewhenthesleeptran-sistorsareturnedoff.
Flautneretal.proposethe“drowsycache”techniquethatswitchesVdddynamically[11].Forshort-channeldevicessuchas0.07µchannellengthdevices,leakagepowerincreasesduetoDrainInducedBarrierLower-ing(DIBL),therebyincreasingsubthresholdleakagecur-rent.ThedrowsycachelowersthesupplyvoltageduringdrowsymodeandsuppressesleakagecurrentusingDIBL.Thedrowsycachetechniquecanretainstoreddataataleakagepowerreductionofupto86%[11].
OursleepystackSRAMcellcanachievemorepowersavingsthanahigh-Vth,anACCoradrowsycacheSRAMcell.Furthermore,thesleepystackSRAMdoesnotrequirelargetransitiontimeandtransitionpowercon-sumptionunlikeABC-MTCMOS.
3Approach
We rstintroduceourrecentlyproposedlow-leakagestructurenamed“sleepystack”inSection3.1.Then,weexplainournewlyproposed“sleepystackSRAM”inSec-tion3.2.
3.1Sleepystackleakagereduction
Thesleepystacktechniquehasastructuremergingtheforcedstacktechniqueandthesleeptransistortechnique.Figure1showsasleepystackinverter.ThesleepystacktechniquepidesexistingtransistorsintotwotransistorseachtypicallywiththesamewidthW1halfthesizeoftheoriginalsingletransistor’swidthW0(i.e.,W1=W0/2),
’=1
’=0
Figure1:(a)Sleepystackinverteractivemode(left)and(b)sleepmode(right)
thusmaintainingequivalentinputcapacitance.ThesleepystackinverterinFigure1(a)usesW/L=3forthepull-uptransistorsandW/L=1.5forthepull-downtransis-tors,whileaconventionalinverterwiththesameinputca-pacitancewoulduseW/L=6forthepull-uptransis-torandW/L=3forthepull-downtransistor(assumingµn=2µp).Thensleeptransistorsareaddedinparalleltooneofthetransistorsineachsetoftwostackedtransistors.Weusehalfsizetransistorwidthoftheoriginaltransistor(i.e.,weuseW0/2)forthesleeptransistorwidthofthesleepystack.
Duringactivemode,S=0andS =1areasserted,andthusallsleeptransistorsareturnedon.Thisstructurepo-tentiallyreducescircuitdelay(comparedtonotaddingsleeptransistors)because(i)addedsleeptransistorsarealwaysonduringactivemodeandthusateachsleeptran-sistordrain,thevoltagevalueconnectedtoasleeptran-sistorisalwaysreadyduringactivemodeand(ii)thereisareducedresistanceduetothetwoparalleltransistors.Therefore,wecanintroducehigh-Vthtransistorstothesleeptransistorsandtransistorsinparallelwiththesleeptransistorwithoutincurringlarge(e.g.,2Xormore)de-layoverhead.Duringsleepmode,S=1andS =0areas-serted,andsobothofthesleeptransistorsareturnedoff.Thehigh-Vthtransistorsandthestackedtransistorsinthesleepystackapproachsuppressleakagecurrent.Inshort,usinghigh-Vthtransistors,thesleepystacktechniquepo-tentiallyachieves200Xleakagereductionovertheforcedstacktechnique.Furthermore,unlikethesleeptransistortechnique[10],thesleepystacktechniquecanretainexactlogicstatewhileachievingsimilarleakagereduction.
3.2SleepystackSRAMcell
Figure2:SRAMcellleakagepaths
WedesignanSRAMcellbasedonthesleepystacktechnique.Theconventional6-TSRAMcellconsistsoftwocoupledinvertersandtwowordlinepasstransistorsasshowninFigure2.Sincethesleepystacktechniquecan
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particula
beappliedtoeachtransistorseparately,thesixtransistorscanbechangedinpidually.However,tobalancecurrent ow(failuretodosopotentiallyincreasestheriskofsofterrors[9]),asymmetricdesignapproachisused.
Table1:SleepystackappliedtoanSRAMcell
Combinations
cell leakagebitline leakagereduction
reductionPull-Down (PD) sleepy stackmediumlowPull-Down (PD), wordline (WL) sleepy stackmediumhighPull-Up (PU), Pull-Down (PD) sleepy stackhighlow
Pull-Up (PU), Pull-Down (PD),
wordline (WL) sleepy stack
high
high
Therearetwomaintypesofsubthresholdleakagecur-rentsina6-TSRAMcell:cellleakageandbitlineleak-age(seeFigure2).Itisveryimportantwhenapply-ingthesleepystacktechniquetoconsiderthevariousleakagepathsintheSRAMcell.Toaddresstheeffectofthesleepystacktechniqueproperly,weconsiderfourcombinationsofthesleepystackSRAMcellasshowninTable1.InTable1,“Pull-Down(PD)sleepystack”meansthatthesleepystacktechniqueisonlyappliedtothepull-downtransistorsofanSRAMcellasindicatedinthebottomdashedboxinFigure3.“Pull-Down(PD),wordline(WL)sleepystack”meansthatthesleepystacktechniqueisappliedtothepull-downtransistorsaswellaswordlinetransistors.Similarly,“Pull-Up(PU),Pull-Down(PD)sleepystack”meansthatthesleepystacktechniqueisappliedtothepull-uptransistorsandthepull-downtransistors(butnottothewordlinetran-sistors)ofanSRAMcell.Finally,“Pull-Up(PU),Pull-Down(PD),wordline(WL)sleepystack”meansthatthesleepystacktechniqueisappliedtoallthetransistorsinanSRAMcell.
ThePDsleepystackcansuppresssomepartofthecellleakage.Meanwhile,thePU,PDsleepystackcansup-pressthemajorityofthecellleakage.However,with-outapplyingthesleepystacktechniquetothewordline(WL)transistors,bitlineleakagecannotbesigni -cantlysuppressed.Althoughlyinginthebitlineleak-agepath,thepull-downsleepystackisnoteffectivetosuppressbothbitlineleakagepathsbecauseoneofthepull-downsleepystacksisalwayson.Therefore,tosup-presssubthresholdleakagecurrentinaSRAMcellfully,thePU,PDandWLsleepystackapproachneedstobeconsideredasshowninFigure3.
ThesleepystackSRAMcelldesignresultsinareain-creasebecauseoftheincreaseinthenumberoftransis-tors.However,wehalvethetransistorwidthsinaconven-tionalSRAMcelltomaketheareaincreaseofthesleepystackSRAMcellnotnecessarilydirectlyproportionaltothenumberoftransistors.Halvingatransistorwidthispossiblewhentheoriginaltransistorwidthisatleast2Xlargerthantheminimumtransistorwidth(whichistypi-callythecaseinmodernhighperformanceSRAMcellde-sign).Unliketheconventional6-TSRAMcell,thesleepystackSRAMcellrequirestheroutingofoneortwoextrawiresforthesleepcontrolsignal(s).
Figure3:SleepystackSRAMcell
4Experimentalmethodology
ToevaluatethesleepystackSRAMcell,wecompareourtechniqueto(i)usinghigh-Vthtransistorsasdirectre-placementsforlow-Vthtransistors(thusmaintainingonly6transistorsinanSRAMcell)and(ii)theforcedstacktechnique[7];wechoosethesetechniquesbecausethesetwotechniquesarestatesavingtechniqueswithouthighriskofsofterror[9].AlthoughAsymmetric-CellSRAMexplainedinSection2isalsoastate-savingSRAMcelldesign,wedonotconsiderAsymmetric-CellSRAMbe-causeweassumethatourSRAMcellsare lledequallywith‘1s’and‘0s.’ThisisnottheconditionthatACCprefers,andunderthisconditiontheleakagepowersav-ingsofACCaresmallerthanthehigh-VthSRAMcell,whichuseshigh-Vthforallsixtransistors.
We rstlayoutSRAMcellsofeachtechnique.Insteadofstartingfromscratch,weusetheCACTImodelfortheSRAMstructureandtransistorsizing[12].WeuseNCSUCadencedesignkittargetingTSMC0.18µtech-nology[13].Byscalingdownthe0.18µlayout,weobtain0.07µtechnologytransistorlevelHSPICEschematics[4],andwedesigna64x64bitSRAMcellarray.
Weestimateareadirectlyfromourcustomlayoutus-ingTSMC0.18µtechnologyandscaleto0.07µusingthefollowingformula:0.07µarea=0.18µarea×(0.07µ)2/(0.18µ)2×1.1(non-linearoverhead)[4].Weareawarethisisnotexact,hencetheword“estimate.”Wealsoas-sumetheareaoftheSRAMcellwithhigh-Vthtransistorsisthesameaswithlow-Vthtransistors.Thisassumptionisreasonablebecausehigh-Vthcanbeimplementedbychanginggateoxidethickness,andthisalmostdoesnotaf-fectareaatall.Weestimatedynamicpower,staticpowerandreadtimeofeachofthevariousSRAMcelldesignsusingHSPICEsimulationwithBerkeleyPredictiveTech-nologyModel(BPTM)targeting0.07µtechnology[14].Thereadtimeismeasuredfromthetimewhenanenabledwordlinereaches10%oftheVddvoltagetothetimewheneitherbitlineorbitline’dropsfrom100%oftheprechargedvoltageto90%oftheprechargedvolt-agevaluewhiletheotherremainshigh.Therefore,oneofthebitlinesignalremainsatVdd,andtheotheris0.9xVdd.This10%voltagedifferencebetweenbitlineandbitline’istypicallyenoughforasenseampli ertodetectthestoredcellvalue[15].Dynamicpowerof
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particula
theSRAMarrayismeasuredduringthereadoperationwithcycletimeof4ns.StaticpoweroftheSRAMcellismeasuredbyturningoffsleeptransistorsifapplicable.Toavoidleakagepowermeasurementbiasedbyamajorityof‘1’versus‘0’(orvice-versa)values,halfofthecellsarerandomlysetto‘0,’withtheremaininghalfofthecellssetto‘1.’
5Results
WecomparethesleepystackSRAMcelltothecon-ventional6-TSRAMcell,high-Vth6-TSRAMcellandforcedstackSRAMcell.Forthe“high-Vth”techniqueandtheforcedstacktechnique,weconsiderthesametech-niquecombinationsweappliedtothesleepystackSRAMcell–seeTable1.
Toproperlyobservethetechniques,wecompare13differentcasesasshowninTable2.Case1istheconven-tional6-TSRAMcell,whichisourbasecase.Cases2,3,4and5are6-TSRAMcellsusingthehigh-Vthtechnique.PDhigh-Vthisthehigh-Vthtechniqueappliedonlytothepull-downtransistors.PD,WLhigh-Vthisthehigh-Vthtechniqueappliedtothepull-downtransistorsaswellastothewordlinetransistors.PU,PDhigh-Vthisthehigh-Vthtechniqueappliedtothepull-upandpull-downtran-sistors.PU,PD,WLhigh-Vthisthehigh-VthtechniqueappliedtoalltheSRAMtransistors.Cases6,7,8and9are6-TSRAMcellswiththeforcedstacktechnique[7].PDstackistheforcedstacktechniqueappliedonlytothepull-downtransistors.PD,WLstackistheforcedstacktechniqueappliedtothepull-downtransistorsaswellastothewordlinetransistors.PU,PDstackistheforcedstacktechniqueappliedtothepull-upandpull-downtran-sistors.PU,PD,WLstackistheforcedstacktechniqueappliedtoalltheSRAMtransistors.Pleasenotethatwedonotapplyhigh-Vthtotheforcedstacktechniquebe-causetheforcedstackSRAMwithhigh-Vthincursmorethan2Xdelayincrease.Cases10,11,12and13arethefoursleepystackSRAMcellapproachesaslistedinTa-ble1.ForsleepystackSRAM,high-VthisappliedonlytothesleeptransistorsandthetransistorsparalleltothesleeptransistorsasshowninFigure3.
5.1Area
Table2:Layoutarea
Technique
Area(u2)Area(u2)Normalized
0.18u20.07u2
areaCase1
Low-Vth Std3.8254.50017.2132.8641.00Case2PD high-Vth
3.8254.50017.2132.8641.00Case3PD, WL high-Vth3.8254.50017.2132.8641.00Case4PU, PD high-Vth
3.8254.50017.2132.8641.00Case5PU, PD, WL high-Vth3.8254.50017.2132.8641.00Case6PD stack
3.4654.68016.2162.6980.94Case7PD, WL stack3.4655.76019.9583.3201.16Case8PU, PD stack
3.2854.68015.3742.5580.89Case9PU, PD, WL stack3.4655.76019.9583.3201.16Case10PD sleepy stack
4.5455.04022.9073.8111.33Case11PD, WL sleepy stack4.4556.70529.8714.9691.74Case12PU, PD sleepy stack
5.7605.04029.0304.8291.69Case13
PU, PD, WL sleepy stack
5.535
6.615
36.614
6.0912.13
Table2showstheareaofeachtechnique.PleasenotethatSRAMcellareacanbereducedfurtherbyusingmini-
mumsizetransistors,butreducingtransistorsizeincreasescellreadtime.SomeSRAMcellswiththeforcedstacktechniqueshowsmallerareaevencomparedtothebasecase.Thereasonisthatpidedtransistorscanenableaparticularlysqueezeddesign[4].Thesleepystacktech-niqueincreasesareabybetween33%and113%.TheaddedsleeptransistorsareabottlenecktoreducethesizeofthesleepystackSRAMcells.Further,wiringthesleepcontrolsignals(anoverheadwedonotconsiderinTa-ble2)makesthedesignmorecomplicated.
5.2Cellreadtime
Table3:Normalizedcellreadtime
Technique25°C
110°C
1xVth1.5xVth2xVth
1xVth1.5xVth2xVth
Case1Low-Vth Std1.000
N/A1.000
N/ACase2PD high-Vth1.0221.0431.0201.061Case3PD, WL high-VthCase4PU, PD high-VthN/A
1.1111.280
1.0221.055N/A
1.1171.262
1.0201.048Case5PU, PD, WL high-Vth1.1111.2771.1101.259
Case6PD stack1.3681.345Case7PD, WL stack1.647
1.682
Case8PU, PD stack1.348N/A
1.341N/A
Case9PU, PD, WL stack1.7041.678
Case10PD sleepy stack1.2761.3071.2631.254Case11PD, WL sleepy stack1.458Case12PU, PD sleepy stackN/A
1.551
1.2751.306N/A
1.4351.546
1.2871.319Case13
PU, PD, WL sleepy stack1.4561.605
1.4501.504
AlthoughSRAMcellreadtimechangesslightlyas
temperaturechanges,theimpactoftemperatureonthecellreadtimeisquitesmall.However,theimpactofthresholdvoltageislarge.Weapply1.5xVthand2xVthforthehigh-Vthtechniqueandthesleepystacktechnique.AsshowninTable3,thedelaypenaltyoftheforcedstacktechnique(withalllow-Vthtransistors)isbetween35%and70%comparedtothestandard6-TSRAMcell.Thisisoneoftheprimaryreasonsthattheforcedstacktechniquecannotusehigh-Vthtransistorswithoutincurringdramaticdelayincrease(e.g.,2Xormoredelaypenaltyisobservedusingeither1.5xVthor2xVth).
Amongthethreelow-leakagetechniques,thesleepystacktechniqueisthesecondbestintermsofcellreadtime.ThePU,PD,WLhigh-Vthwith2xVthis16%fasterthanthePU,PD,WLsleepystackwith2xVthat110o.SinceweareawarethatareaanddelayarecriticalfactorswhendesigningSRAM,wewillexploreareaanddelayimpactusingtradeoffsinSection5.4.However,letus rstdiscussleakagereduction(i.e.,withoutyetfocusingontradeoffs,whichwillbethefocusofSection5.4).
5.3Leakagepower
Wemeasureleakagepowerwhilechangingthresholdvoltageandtemperaturebecausetheimpactofthresholdvoltageandtemperatureonleakagepowerissigni cant.Table4showsleakagepowerconsumptionwithtwohigh-Vthvalues,1.5xVothand2xVth,andtwotemperatures,25Cand110oC,whereCase1andthecasesusingtheforcedstacktechnique(Cases6,7,8and9)arenotaf-fectedbychangingVthbecausetheseuseonlylow-Vth.(Pleasenotetheabsolutenumbersareavailablein[4].)
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particula
Table4:Normalizedleakagepower
Normalized leakage powerTechnique
25°C110°C
1xVth1.5xVth2xVth1xVth1.5xVth2xVth
Case1Low-Vth Std1.0000N/A1.0000N/ACase2PD high-Vth
0.54660.52740.57110.5305Case3PD, WL high-Vth0.1860
Case4PU, PD high-Vth
N/A0.20710.17360.25550.37850.3552N/A
0.40220.3522Case5PU, PD, WL high-Vth0.03910.00140.08570.0065
Case6PD stack
0.55410.5641Case7PD, WL stack0.2213Case8PU, PD stack
0.3862N/A
0.2554
0.3950N/ACase9PU, PD, WL stack0.05550.0832
Case10PD sleepy stack
0.53310.53150.52820.5192Case11PD, WL sleepy stack0.18520.1827Case12PU, PD sleepy stack
N/A
0.36460.3630N/A
0.19550.1820
0.35340.3439Case13
PU, PD, WL sleepy stack
0.01670.00330.01670.0024
5.3.1
Resultsat25oC
Ourresultsat25oCshowthatCase5isthebestwith2xVth
andCase13isthebestwith1.5xVth.Specially,at1.5xVth,Case5andCase13achieve25Xand60Xleakagereduc-tionoverCase1,respectively.However,theleakagere-ductioncomeswithdelayincrease.Thedelaypenaltyis11%and45%,respectively,comparedtoCase1.5.3.2
Resultsat110o
C
Absolutepowerconsumptionnumbersat110o
Cshow
morethan10Xincreaseofleakagepowerconsumptioncomparedtotheresultsat25oC.ThiscouldbeaseriousproblemforSRAMbecauseSRAMoftenresidesnexttoamicroprocessorwhosetemperatureishigh.
At110oC,thesleepystacktechniqueshowsthebestre-sultinboth1.5xVthand2xVthevencomparedtothehigh-Vthtechnique.Theleakageperformancedegradationun-derhightemperatureisverynoticeablewiththehigh-Vthtechniqueandtheforcedstacktechnique.Forexample,at25oCthehigh-Vthtechniquewith1.5xVth(Case5)andtheforcedstacktechnique(Case9)showaround96%leak-agereduction.However,at110oCthesametechniquesshowaround91%ofleakagepowerreductioncomparedtoCase1.Onlythesleepystacktechniqueachievessu-periorleakagepowerreduction;afterincreasingtemper-ature,thesleepystackSRAMshows5.1Xand4.8Xre-ductionscomparedtoCase5andCase9,respectively,with1.5xVth.
Whenthelow-leakagetechniquesareappliedonlytothepull-upandpull-downtransistors,leakagepowerreductionisatmost65%(2xVth,110oC)becausebitlineleakagecannotbesuppressed.Theremaining35%ofleakagepowercanbesuppressedbyapplyinglow-leakagetechniquestowordlinetransistors.Thisim-pliesthatbitlineleakagepoweraddressesaround35%ofSRAMcellleakagepowerconsumption.Thistrendisobservedforallthreetechnniquesconsidered,i.e.,high-Vth,forcedstackandsleepystack.
5.4Tradeoffsinlow-leakagetechniques
Althoughthesleepystacktechniqueshowssuperiorre-sultsintermsofleakagepower,weneedtoexplorearea,delayandpowertogetherbecausethesleepystacktech-
niquecomeswithnon-negligibleareaanddelaypenalties.Tobecomparedwiththehigh-Vthtechniqueatthesamecellreadtime,weconsiderfourmorecasesforsleepystackSRAMinadditiontothecasesalreadyconsideredinTable4;weincreasethewidthsofallwordlineandpull-downtransistors(includingsleeptransistors).Specif-ically,forthesleepystacktechnique,we ndnewtransis-torwidthsofwordlinetransistorsandpull-downtran-sistorssuchthattheresultisdelayapproximatelyequaltothedelayofthe6-Thigh-Vthcase,i.e.,Case5.Thenewcasesaremarkedwith‘*’(Cases10*,11*,12*,13*).TheresultsareshowninTable5.Toenhancereadabilityoftradeoffs,eachtableissortedbyleakagepower.Althoughwecomparedfourdifferentsimulationconditions,wetaketheconditionwith2xVthat110oCand2xVthat110oCasimportantrepresentativetechnologypointsatwhichtocomparethetrade-offsbetweentechniques.Wechoose110oCbecausegenerallySRAMoperatesatahightem-peratureandalsobecausehightemperatureisthe“worstcase.”
Table5:Tradeoffs(2xVth,110oC)
Technique
NormalizedNormalizedNormalizedleakagedelayarea
Case1Low-Vth Std1.0001.0001.000Case6PD stack0.5641.3450.942Case2PD high-Vth0.5301.0611.000Case10PD sleepy stack0.5191.2541.331Case10*PD sleepy stack*0.5191.2541.331Case8PU, PD stack0.3951.3410.893Case4PU, PD high-Vth0.3521.0481.000Case12*PU, PD sleepy stack*0.3441.2701.713Case12PU, PD sleepy stack0.3441.3191.687Case7PD, WL stack0.2551.6821.159Case3PD, WL high-Vth0.1861.2621.000Case11*PD, WL sleepy stack*0.1831.2391.876Case11PD, WL sleepy stack0.1821.5461.735Case9PU, PD, WL stack0.0831.6781.159Case5PU, PD, WL high-Vth0.0071.2591.000Case13*PU, PD, WL sleepy stack*0.0031.2652.253Case13
PU, PD, WL sleepy stack
0.0021.5042.127
InTable5,weobservesixParetopoints,respectively,whichareinshadedrows,consideringthreevariablesofleakage,delay,andarea.Case13showsthelowestpossi-bleleakage,2.7Xsmallerthantheleakageofanyofthepriorapproachesconsidered;however,thereisacorre-spondingdelayandareapenalty.Alternatively,Case13*showsthesamedelay(within0.2%)asCase5and2.26XleakagereductionoverCase5;however,Case13*uses125%moreareathanCase5.Inshort,thispaperpresentsnew,previouslyunknownParetopointsatthelow-leakageendofthespectrum(forade nitionofa“Paretopoint,”pleasesee[16]).
5.5Activepower
Table6showspowerconsumptionduringreadopera-tions.TheactivepowerconsumptionincludesdynamicpowerusedtochargeanddischargeSRAMcellsplusleakagepowerconsumption.At25oCleakagepowerislessthan20%oftheactivepowerincaseofthestan-dardlow-VthSRAMcellin0.07µtechnologyaccording
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particula
Table6:Normalizedactivepower
Technique
25°C
110°C
1xVth1.5xVth2xVth
1xVth1.5xVth2xVth
Case1Low-Vth Std1.000
N/A1.000
N/ACase2PD high-Vth0.9360.9130.7240.691Case3PD, WL high-VthCase4PU, PD high-VthN/A
0.8580.829
0.9280.893N/A
0.6180.478
0.5720.582Case5PU, PD, WL high-Vth0.8380.8420.4320.368
Case6PD stack0.9260.669Case7PD, WL stack0.665
0.398
Case8PU, PD stack0.905N/A
0.596N/A
Case9PU, PD, WL stack0.6370.293
Case10PD sleepy stack0.9810.9810.8070.811Case11PD, WL sleepy stack0.773Case12PU, PD sleepy stackN/A
0.717
0.9611.005N/A
0.5860.600
0.7860.797Case13
PU, PD, WL sleepy stack0.7190.708
0.5880.546
toBPTM[14].However,leakagepowerincreases10Xasthetemperaturechangesto110oCalthoughactivepowerincreases3X.At110oC,leakagepowerismorethanhalfoftheactivepowerfromoursimulationresults.There-fore,withoutaneffectiveleakagepowerreductiontech-nique,totalpowerconsumption–eveninactivemode–isaffectedsigni cantly.
5.6Staticnoisemargin
ChangingtheSRAMcellstructuremaychangethestaticnoiseimmunityoftheSRAMcell.Thus,wemea-suretheStaticNoiseMargin(SNM)ofthesleepystackSRAMcellandtheconventional6-TSRAMcell.TheSNMisde nedbythesizeofthemaximumnestedsquareinabutter yplot.TheSNMofthesleepystackSRAMcellismeasuredtwiceinactivemodeandsleepmode.TheSNMofthesleepystackSRAMcellinactivemodeis0.299VandalmostexactlythesameastheSNMofacon-ventionalSRAMcell;theSNMofaconventionalSRAMcellis0.299V.Althoughwedonotperformaprocessvariationanalysis,weexpectthatthehighSNMofthesleepystackSRAMcellmakesthetechniqueasimmunetoprocessvariationsasaconventionalSRAMcell.
6Conclusionsandfuturework
Inthispaperwehavepresentedandevaluatedournewlyproposed“sleepystackSRAM.”OursleepystackSRAMprovidesthelargestleakagesavingsamongallal-ternativesconsidered.Speci cally,comparedtoastan-dardSRAMcell–Case1–Table4showsthatat110oCand2xVth,Case13reducesleakageby424XascomparedtoCase1;unfortunately,this424Xreductioncomesasacostofadelayincreaseof50.4%andanareapenaltyof113%.ResizingthesleepystackSRAMcanreducedelaysigni cantlyatacostoflessleakagesavings;speci cally,Case13*isaninterestingParetopointasdiscussedinSec-tion5.4.
Webelievethatthispaperpresentsanimportantde-velopmentbecauseoursleepystackSRAMseemstopro-vide,ingeneral,thelowestleakageParetopointsofanyVLSIdesignstyleknowntotheauthors.Giventhenon-trivialareapenalty(e.g.,upto125%forCase13*inTa-ble5),perhapssleepystackSRAMwouldbemostap-propriateforasmallSRAMintendedtostoreminimalstandbydataforanembeddedsystemspendingsigni -
canttimeinstandbymode;forsuchasmallSRAM(e.g.,
16KB),theareapenaltymaybeacceptablegivensystem-levelstandbypowerrequirements.Ifabsoluteminimumleakagepowerisextremelycritical,thenperhapsspeci ctargetembeddedsystemscouldusesleepystackSRAMmorewidely.
Forfuturework,wewillexplorehowprocessvaria-tionsaffectleakagepowerreductionusingsleepystackSRAM.
7References
[1]InternationalTechnologyRoadmapforSemiconductorsbySemi-conductorIndustryAssociation,2002.[Online].Availablehttp://www.77cn.com.cn.[2]N.S.Kim,T.Austin,D.Baauw,T.Mudge,K.Flautner,J.Hu,
M.Irwin,M.Kandemir,andV.Narayanan,“LeakageCurrent:Moore’sLawMeetsStaticPower,”IEEEComputer,vol.36,pp.68–75,December2003.[3]L.Clark,E.Hoffman,J.Miller,M.Biyani,L.Luyun,S.Straz-dus,M.Morrow,K.Velarde,andM.Yarch,“AnEmbedded32-bMicroprocessorCoreforLow-PowerandHigh-PerformanceAp-plications,”IEEEJournalofSolid-StateCircuits,vol.36,no.11,pp.1599–1608,November2001.[4]J.Park,“SleepyStack:aNewApproachtoLowPowerVLSI
andMemory,”Ph.D.dissertation,SchoolofElectricalandComputerEngineering,GeorgiaInstituteofTechnology,2005.[Online].Availablehttp://etd.gatech.edu/theses/available/etd-07132005-131806/.[5]N.Azizi,A.Moshovos,andF.Najm,“Low-LeakageAsymmetric-CellSRAM,”ProceedingsoftheInternationalSymposiumonLowPowerElectronicsandDesign,pp.48–51,August2002.[6]K.Nii,H.Makino,Y.Tujihashi,C.Morishima,Y.Hayakawa,
H.Nunogami,T.Arakawa,andH.Hamano,“ALowPowerSRAMUsingAuto-Backgate-ControlledMT-CMOS,”Proceed-ingsoftheInternationalSymposiumonLowPowerElectronicsandDesign,pp.293–298,August1998.[7]S.Narendra,V.D.S.Borkar,D.Antoniadis,andA.Chandrakasan,
“ScalingofStackEffectanditsApplicationforLeakageReduc-tion,”ProceedingsoftheInternationalSymposiumonLowPowerElectronicsandDesign,pp.195–200,August2001.[8]S.Tang,S.Hsu,Y.Ye,J.Tschanz,D.Somasekhar,S.Narendra,
S.-L.Lu,R.Krishnamurthy,andV.De,“ScalingofStackEffectanditsApplicationforLeakageReduction,”SymposiumonVLSICircuitsDigestofTechnicalPapers,pp.320–321,June2002.[9]V.Degalahal,N.Vijaykrishnan,andM.Irwin,“Analyzingsoft
errorsinleakageoptimizedSRAMdesign,”IEEEInternationalConferenceonVLSIDesign,pp.227–233,January2003.[10]M.Powell,S.-H.Yang,B.Falsa ,K.Roy,andT.N.Vijaykumar,
“Gated-Vdd:ACircuitTechniquetoReduceLeakageinDeep-submicronCacheMemories,”ProceedingsoftheInternationalSymposiumonLowPowerElectronicsandDesign,pp.90–95,July2000.[11]K.Flautner,N.S.Kim,S.Martin,D.Blaauw,andT.Mudge,
“DrowsyCaches:SimpleTechniquesforReducingLeakagePower,”ProceedingsoftheInternationalSymposiumonComputerArchitecture,pp.148–157,May2002.[12]S.WiltonandN.Jouppi,AnEnhancedAccessandCy-cleTimeModelforOn-ChipCaches.[Online].Availablehttp://www.77cn.com.cn/wrl/people/jouppi/CACTI.html.[13]NCStateUniversityCadenceToolInformation.[Online].Avail-ablehttp://www.cadence.ncsu.edu.[14]BerkeleyPredictiveTechnologyModel(BPTM).[Online].Avail-ablehttp://www-device.eecs.berkeley.edu/ ptm/.[15]N.Azizi,A.Moshovos,andF.Najm,“Low-LeakageAsymmetric-CellSRAM,”ProceedingsoftheInternationalSymposiumonLowPowerElectronicsandDesign,pp.48–51,August2002.[16]G.D.Micheli,SynthesisandOptimizationofDigitalCircuits.
USA:McGraw-HillInc.,1994.
