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should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.
·XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
·XTAL2：Output from the inverting oscillator amplifier.
·Ready/BUSY: The progress of byte programming can also be monitored by the RDY/BSYoutput signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Oscillator Characteristics：
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used.
To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven.
There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide by two flip trigger, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode：
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down Mode:
In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and special function registers retain their values until the power-down mode is terminated. The only exit from power-down is
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中原工学院信息商务学院外文翻译
a hardware reset. Reset redefines the special function registers but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits:
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Programming the Flash:
The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled.
The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program any nonblank byte in the on-chip Flash memory, the entire memory must be erased using the chip erase mode. Programming Algorithm:
Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table .To program the AT89C51, take the following steps:
1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
5. Pulse ALE/PROGonce to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling:
The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and
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中原工学院信息商务学院外文翻译
the next cycle may begin. Data polling may begin any time after a write cycle has been initiated.
Program Verify:
If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase:
The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes:
The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows:
(030H) = 1EH indicates manufactured by ATMEL (031H) = 51H indicates AT89C51 single-chip (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface:
Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. （2）The sensor DS18B20
In the traditional analog signal distance temperature measuring system, need good solve lead error compensation, multi-point measurement error and amplifying circuit switching technologies such as zero drift error problem, can achieve high measuring accuracy. Another general monitoring site of the electromagnetic environment is very bad, all kinds of jamming signal is stronger, the simulated temperature signal interference and vulnerable to produce measurement error and measuring precision [5]. Therefore, in temperature measuring system, the strong anti-jamming capability of the new digital temperature sensor is the most effective to solve these problems, compared with other temperature sensor DSl820 has the following features:
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中原工学院信息商务学院外文翻译
(1) the unique singleline interface way. DSl820 in connection with the microprocessor only need one interface to implement line DSl820 microprocessors and two-way communication. (2) more function simplifies distributed temperature detection application. (3) DSl820 in use without any peripheral devices. (4) power, voltage range data available from 3.0 V to 5.5 V. (5) can measure temperature range from - 55 degrees c + + to 125, incremental value 0. 5 ° c, Fahrenheit temperature range from - 67 to + 257, incremental value 0.9. (6) support multi-point network function. Multiple DS1820 can pick on the same bus and, more temperature measurement. (7) 9 temperature resolution. Measuring results in nine serial transmission way the digital quantity. (8) user can set temperature alarm threshold. (9) have super temperature search function.
①.DSl8B20 principle of work
The internal structure of DS18B20 DSl8B20 temperature measurement principle diagram shown in figure 3.2. Low temperature coefficient graph oscillation frequency vibration product temperature is used to produce with fixed frequency, pulse signal to counter l. High temperature coefficient crystals temperature-dependent its oscillation frequency change significantly. The signal generated as the counter 2 input pulses. Counter 1, 2 and temperature registers are counter in - 55 degrees preset corresponding a base value. Counter l to low temperature coefficient of the pulse signal generated crystals, when the counter for subtraction counting the preset value reduced to 1, when the temperature counter O value will add l, counter the preset value will be l man again, to counter the l start low temperature coefficient of crystal oscillator pulse signal, so cycle count until the counter 2, stop counting to O accumulative temperature, temperature of the register for the register is measured values. Figure 3.2 accumulative used for the slope compensation and fixed temperature measurement, the output of the process of nonlinear correction is less than the preset value counter l. ②.AT89C51 interface mode and DS18B20
Chip DS18B20 and the connection has two kinds: namely parasitic power and external power supply mode.
Parasitic power way: in the parasitic power supply mode, the signal from the single chip DS18B20 in line drawing energy during the high level in the DQ energy stored in the internal capacitance, low level in signal in the energy consumed during the capacitance on working until high-level coming again to parasitic power (battery). Parasitic power mode has three
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