loadingstate<=s2;--无中断请求 end if;
when s1=>----读入读出选择
if RW='1' and A0='1' then--cpu写入数据到BR BR<=DIN; SR(7)<='0'; state<=s2;
elsif RW='0' and A0='0' then--cpu读入SR的数据 DOUT<=SR;
elsif RW='1' and A0='0' then--cpu写入数据到SR SR<=DIN;
elsif RW='0' and A0='1' then--cpu读入BR的数据 DOUT<=BR; end if; when s2=>----打印机
if RDY='1' then TR<='1'; PD<=BR;
SR(7)<='1'; end if;
state<=s0; end case; end if;
end process;
end Behavioral;
the program of printer: library IEEE;
use Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values
--use Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use print is port (
RDY : out std_logic:='1'; TR : in std_logic;
PD : in std_logic_vector(7 downto 0); clk : in std_logic );
end print;
architecture Behavioral of print is signal count: integer range 0 to 5:=0;
signal data: std_logic_vector(7 downto 0); signal ready:std_logic; begin
process(clk,TR) begin
if clk'event and clk='1' then if TR='1' then RDY<='0'; ready<='0'; data<=PD; else
if ready='0' then count<=count+1; if count=5 then RDY<='1'; ready<='1'; count<=0; end if; end if; end if; end if;
end process;
end Behavioral;
connection program:
library IEEE;
use Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values
--use Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use top is port (
CLK : in std_logic );
end top;
architecture Behavioral of top is signal a0:std_logic; signal irq:std_logic;
signal d1:std_logic_vector(7 downto 0); signal d2:std_logic_vector(7 downto 0); signal rw:std_logic; signal rdy:std_logic;
signal pd:std_logic_vector(7 downto 0); signal tr:std_logic;
component processor port (
clk : in std_logic; IRQ : in std_logic;
DOUT : out std_logic_vector(7 downto 0):=\ RW : out std_logic:='0';--0read,1write A0 : out std_logic:='0';--0sr,1br
DIN : in std_logic_vector(7 downto 0) );
end component;
component poc port (
A0 : in std_logic; RW : in std_logic; clk : in std_logic; CS : in std_logic:='1'; RDY : in std_logic;
IRQ : out std_logic:='1';
DOUT : out std_logic_vector(7 downto 0); PD : out std_logic_vector(7 downto 0); TR : out std_logic:='0';
DIN : in std_logic_vector(7 downto 0) );
end component;
component print port (
RDY : out std_logic:='1';
TR : in std_logic;
PD : in std_logic_vector(7 downto 0); clk : in std_logic );
end component; begin
u1: processor port map(clk=>CLK,A0=>a0,RW=>rw,IRQ=>irq,DOUT=>d1,DIN=>d2); u2: poc port
map(clk=>CLK,A0=>a0,RW=>rw,IRQ=>irq,DOUT=>d2,DIN=>d1,RDY=>rdy,TR=>tr,PD=>pd);
u3: print port map(clk=>CLK,RDY=>rdy,TR=>tr,PD=>pd); end Behavioral;