SERIAL ARCHITECTURE FOR HIGH ASSURANCE PROCESSING

SERIAL ARCHITECTURE FOR HIGH ASSURANCE

PROCESSING

申请(专利)号： US20100713409

专利号： US2011213984A1 主分类号： H04L9/32 申请权利人： GERARDO

ORLANDO;

DAVID R. KING; MARK

KRUMPOCH;

EVAN CUSTODIO 公开国代码： US 优先权国家： US

摘 要：

A processing system (60)

includes an input interface (62), a first processor (64), a second processor (66), and an output interface (68) arranged in a serial configuration. Each of the input interface (62), first processor (64), second processor (66), and output interface

(68) computes a digest (92, 100, 110, and 114) using

information, e.g., a unique parameter (94, 102, 112, 118), known only by that element (62, 64, 66, 68) and using information generated by that element (62, 64, 66, 68). The digests (92, 100, 110, and 114) are used to validate the integrity of payload data (86) processed by the system (60) to form processed data (104) and

申请日： 2010-02-26 公开公告日： 2011-09-01

分类号： H04L9/32

发明设计人： GERARDO

ORLANDO;

EVAN CUSTODIO; DAVID R. KING; MARK KRUMPOCH 申请国代码： US

优先权： 20100226 US

71340910

摘 要 附 图：

the system (60) only outputs the processed data (104) upon validation of data integrity. The serial

configuration of system (60) may be implemented to provide high bit rate, redundant cryptographic services. 主权项：

1. A method of processing payload data in a serial arrangement of processors, said

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