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On-chip series termination without calibrationOn-chip parallel termination with calibration (OCT RT)On-chip differential termination (OCT RD)PCI clamping diode
The I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output-enable (OE) path for handling the OE signal for the output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchronization. The input path consists of the DDR input registers, alignment and synchronization registers, and HDR. You can bypass each block of the input path. Figure7–7 shows the StratixIII IOE structure.
Figure7–7.IOE Structure for Stratix III Devices(Note1), (2)
Firm CoreDQS Logic BlockOE RegisterPRNDQD5_OCTD6_OCTDynamic OCT Control (2)OE
fromCore
2 Half Data Rate BlockAlignment RegistersOE RegisterPRNDQD5, D6DelayVCCIOVCCIOPCI ClampProgrammablePull-Up ResistorWriteDatafromCore
Output Register4Half Data Rate BlockAlignment RegistersPRNDQProgrammable Current Strength and Slew RateControlD5, D6DelayFrom OCTCalibrationBlockOutput BufferOn-ChipTerminationOutput RegisterDPRNQOpen DrainD2 DelayD3_0DelayInput BufferclkoutToCoreToCore
D3_1DelayD1DelayBus-HoldCircuitInput RegisterPRNDQReadDatatoCore
4Half Data Rate BlockAlignment andSynchronization RegistersInput RegisterPRNDQInput RegisterPRNDQDQSCQnclkin
D4 DelayNotes to Figure7–7:
(1)D3_0 and D3_1 delays have the same available settings in the Quartus?II software. (2)One dynamic OCT control is available per DQ/DQS group.
The output and OE paths are divided into output or OE registers, alignment registers, and HDR blocks. You can bypass each block of the output and OE path.
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For more information about I/O registers and how they are used for memory applications, refer to the External Memory Interfaces in StratixIII Devices chapter.
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
StratixIII I/O Structure
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O FeaturesStratixIII I/O Structure
Programmable Differential Output Voltage
StratixIII LVDS transmitters support programmable VOD. The programmable VOD settings enable you to adjust output eye height to optimize for trace length and power consumption. A higher VOD swing improves voltage margins at the receiver end while a smaller VOD swing reduces power consumption. The QuartusII software allows four settings for programmable VOD—low, medium low, medium high, and high. The default setting is medium low.
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For more information about programmable VOD, refer to the High Speed Differential I/O Interfaces with DPA inthe StratixIII Devices chapter.
MultiVolt I/O Interface
The StratixIII architecture supports the MultiVoltTM I/O interface feature that allows StratixIII devices in all packages to interface with systems of different supply voltages.
You can connect the VCCIO pins to a 1.2-, 1.5-, 1.8-, 2.5-, 3.0 or 3.3-V power supply, depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply. (For example, when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems.)
You must connect the StratixIII VCCPD power pins to a 2.5-, 3.0 or 3.3-V power supply. Using these power pins to supply the pre-driver power to the output buffers increases the performance of the output pins. Table7–7 summarizes StratixIII MultiVolt I/O support. 1
For VCCIO = 3.3 V, VCCPD=3.3 V. For VCCIO = 3.0 V, VCCPD = 3.0 V. For VCCIO = 2.5 V or less, VCCPD = 2.5 V.
Table7–7.MultiVolt I/O Support for Stratix III Devices(Note1), (2)
Input Signal (V)VCCIO (V)1.21.51.82.53.03.31.2v—————1.5—vv———1.8—v (1)v———2.5———vvv3.0———v (2)vv3.3———v (2)vv1.2v—————1.5—v————Output Signal (V)1.8——v———2.5———v——3.0————v—3.3—————vNotes to Table7–7:
(1)The pin current may be slightly higher than the default value. You must verify that the driving device’s VOL maximum and VOH minimum voltages
do not violate the applicable StratixIII VIL maximum and VIH minimum voltage specifications.
(2)Use on-chip PCI clamp diode for column I/Os or external PCI clamp diode for row I/Os to protect the input pins against overshoot voltage.(3)Each I/O bank of a Stratix III device has its own VCCIO pins and supports only one Vccio, either 1.2, 1.5, 1.8, or 3.0V. The LVDS I/O standard
requires that a VCCIO of 2.5V cannot be assigned in a same bank with a 3.0-V or 3.3-V output signal.
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O FeaturesOCT Support
Dynamic OCT
StratixIII devices support on-off dynamic series and parallel termination for a bi-directional I/O in all I/O banks. Figure7–11 shows the termination schemes supported in the StratixIII device. Dynamic parallel termination is enabled only
when the bi-directional I/O acts as a receiver and is disabled when it acts as a driver. Similarly, dynamic series termination is enabled only when the bi-directional I/O acts as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bi-directional path because the signal integrity is optimized depending on the direction of the data.
You should connect a bi-directional pin that uses both 25-Ω or 50-Ω series termination and 50-Ω input termination to a calibration block that has a 50-Ω external resistor connected to its RUP and RDN pins. The 25-Ω series termination on the bi-directional pin is achieved through internal divide by two circuits.
Figure7–11.Dynamic Parallel OCT in StratixIII Devices
VCCIOTransmitter100 50 100 ZO = 50 100 50 VCCIO100 ReceiverGNDStratix III OCTGNDStratix III OCTReceiver50 VCCIO100 ZO = 50 100 100 100 VCCIO50 GNDGNDStratix III OCTTransmitterStratix III OCTf
For more information about tolerance specifications for OCT with calibration, refer to the DC and Switching Characteristics of StratixIII Devices chapter.
Stratix III Device Handbook, Volume 1
Chapter 7:StratixIII Device I/O Features
OCT Support
LVDS Input On-Chip Termination (RD)
StratixIII devices support OCT for differential LVDS input buffers with a nominal resistance value of 10Ω, as shown in Figure7–12. You can enable OCTRD in row I/O banks when VCCIO and VCCPD are set to 2.5V. The column I/O banks do not support OCT RD. The dedicated clock input pairs CLK[1,3,8,10][p,n], PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of the StratixIII devices do not support OCT RD. Dedicated clock input pairs
CLK[0,2,9,11][p,n] on row I/O banks support OCT RD. Dedicated clock input pairs CLK[4,5,6,7][p,n] and CLK[12,13,14,15][p,n] on column I/O banks do not support OCT RD.
Figure7–12.Differential Input On-Chip Termination
TransmitterReceiverZO = 50 ΩZO = 50 Ω100 Ω f
For more information about OCT RD, refer to the High Speed Differential I/O Interfaces with DPA in StratixIII Devices chapter.
Table7–11 lists the assignment name and its value for OCT RD in the QuartusII software Assignment Editor.
1
You must set the VCCIO to 2.5V when OCT RD is used for the LVDS input buffer, even if the LVDS input buffer is powered by VCCPD.
Table7–11.On-Chip Differential Termination in QuartusII Software Assignment Editor
Assignment NameAllowed ValuesParallel 50Ω with calibrationInput Termination (Accepts wildcards/groups)DifferentialSeries 25Ω without calibrationSeries 50Ω without calibrationOutput TerminationSeries 25Ω with calibrationSeries 40Ω with calibrationSeries 50Ω with calibrationSeries 60Ω with calibrationOutput buffers for single-ended LVTTL/LVCMOS and HSTL/SSTL standards as well as differential HSTL/SSTL standards.Applies ToInput buffers for single-ended and differential-HSTL/SSTL standardsInput buffers for LVDS receivers on row I/O banks.Stratix III Device Handbook, Volume 1