loadingMemory Modes
ArriaII memory blocks allow you to implement fully synchronous SRAM memory in multiple modes of operation. M9K and M144K blocks do not support asynchronous memory (unregistered inputs). MLABs support asynchronous (flow-through) read operations.
Depending on which memory block you target, you can use the following modes:
■■■■■■
“Single-Port RAM Mode” on page3–10“Simple Dual-Port Mode” on page3–12“True Dual-Port Mode” on page3–15“Shift-Register Mode” on page3–17“ROM Mode” on page3–18“FIFO Mode” on page3–18
1
To choose the desired read-during-write behavior, set the read-during-write behavior to either new data, old data, or don't care in the RAM MegaWizard Plug-In Manager in the Quartus II software. For more information about this behavior, refer to “Read-During-Write Behavior” on page3–21.
When using the memory blocks in ROM, single-port, simple dual-port, or true
dual-port mode, you can corrupt the memory contents if you violate the setup or hold time on any of the memory block input registers. This applies to both read and write operations.
1
Single-Port RAM Mode
All memory blocks support single-port mode. Single-port mode allows you to do either a one-read or a one-write operation at a time. Simultaneous reads and writes are not supported in single-port mode. Figure3–9 shows the single-port RAM configuration.
Figure3–9.Single-Port Memory (Note1)
data[ ]address[ ]wrenbyteena[]addressstall inclockclockenardenaclrNote to Figure3–9:
(1)You can implement two single-port memory blocks in a single M9K and M144K blocks. For more information, refer
to “Packed Mode Support” on page3–5.
q[]outclockArria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 3:Memory Blocks in Arria II DevicesMemory Modes
During a write operation, the RAM output behavior is configurable. If you use the read-enable signal and perform a write operation with the read enable deactivated, the RAM outputs retain the values they held during the most recent active read enable. If you activate read enable during a write operation, or if you do not use the read-enable signal at all, the RAM outputs show the “new data” being written, the “old data” at that address, or a “don’t care” value.
Table3–4 lists the possible port width configurations for memory blocks in single-port mode.
Table3–4.Port Width Configurations for MLABs, M9K, and M144K Blocks (Single-Port Mode)
Port Width Configurations
MLABs
M9K Blocks8K×1
64×864×964×1032×1632×1832×20
4K×22K×41K×81K×9512×16512×18256×32256×36
M144K Blocks16K×816K×98K×168K×184K×324K×362K×642K×72
Figure3–10 shows timing waveforms for read and write operations in single-port mode with unregistered outputs for M9K and M144K blocks. Registering the M9K and M144K block outputs delay the q output by one clock cycle.
Figure3–10.Timing Waveform for Read-Write Operations for M9K and M144K Blocks (Single-Port Mode)
clk_awrenardenaaddress_aa0a1data_aABCDEFq_a (asynch)a0(old data)ABa1(old data)DEArria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 3:Memory Blocks in Arria II Devices
Memory Modes
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 3:Memory Blocks in Arria II DevicesMemory Modes
Simple dual-port mode supports different read and write data widths (mixed width support). Table3–5 lists the mixed width configurations for the M9K blocks in simple dual-port mode. MLABs do not have native support for mixed width operations. The QuartusII software can implement mixed width memories in MLABs with more than one MLAB.
Table3–5.M9K Block Mixed-Width Configurations (Simple Dual-Port Mode)
Read Port
8K×1
8K×14K×22K×41K×8512×16256×321K×9512×18256×36
vvvvvv———
4K×2vvvvvv———
2K×4vvvvvv———
1K×8vvvvvv———
Write Port512×16vvvvvv———
256×32vvvvvv———
1K×9——————vvv
512×18——————vvv
256×36——————vvv
Table3–6 lists the mixed-width configurations for M144K blocks in simple dual-port mode.
Table3–6.M144K Block Mixed-Width Configurations (Simple Dual-Port Mode)
Read Port
16K×8
16K×88K×164K×322K×6416K×98K×184K×362K×72
vvvv————
8K×16vvvv————
4K×32vvvv————
Write Port2K×64vvvv————
16K×9————vvvv
8K×18————vvvv
4K×36————vvvv
2K×72————vvvv
In simple dual-port mode, M9K and M144K blocks support separate write-enable and read-enable signals. Read-during-write operations to the same address can either output a “don’t care” or “old data” value.
MLABs only support a write-enable signal. Read-during-write behavior for the
MLABs can be either a “don’t care” or “old data” value. The available choices depend on the configuration of the MLAB.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 3:Memory Blocks in Arria II Devices
Memory Modes
Figure3–13 shows timing waveforms for read and write operations in simple
dual-port mode with unregistered outputs for M9K and M144K blocks. Registering the M9K and M144K block outputs delay the q output by one clock cycle.
Figure3–13.Simple Dual-Port Timing Waveforms for M9K and M144K Blocks
wrclockwrenwraddressdata rdclockrden rdaddressq (asynch)bndoutn-1b0doutnb1dout0b2b3an-1din-1andina0a1a2a3a4din4a5din5a6din6Figure3–14 shows the timing waveforms for read and write operations in simple dual-port mode with unregistered outputs in the MLAB. The write operation is triggered by the falling clock edges.
Figure3–14.Simple Dual-Port Timing Waveforms for MLABs
wrclockwrenwraddressdata rdclockrden rdaddressq (asynch)bndoutn-1b0doutnb1dout0b2b3an-1din-1andina0a1a2a3a4din4a5din5a6din6Arria II Device Handbook Volume 1: Device Interfaces and Integration