loadingUsing the RUP and RDN Pins in a DQ/DQS Group Used for Memory Interfaces in ArriaIIGZ Devices
You can use the DQS/DQSn pins in some of the ×4 groups as RUP and RDN pins (listed in the pin table). You cannot use a ×4 DQ/DQS group for memory interfaces if any of its pin members are used as RUP and RDN pins for OCT calibration. You may be able to use the ×8/×9 group that includes this ×4 DQ/DQS group, if either of the following applies:
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You are not using DM pins with your differential DQS pinsYou are not using complementary or differential DQS pins
You can use the ×8/×9 group because a DQ/DQS ×8/×9 group actually comprises 12 pins, because the groups are formed by stitching two DQ/DQS groups in ×4 mode with six pins each (refer to Table7–1 on page7–5). A typical ×8 memory interface consists of one DQS, one DM, and eight DQ pins that add up to 10 pins. If you choose your pin assignment carefully, you can use the two extra pins for RUP and RDN. In a DDR3SDRAM interface, you must use differential DQS, which means that you only have one extra pin. In this case, pick different pin locations for the RUP and RDN pins (for example, in the bank that contains the address and command pins).
You cannot use the RUP and RDN pins shared with DQ/DQS group pins when using ×9 QDRII+/QDRII SRAM devices, because the RUP and RDN pins are dual purpose with the CQn pins. In this case, pick different pin locations for RUP and RDN pins to avoid conflict with memory interface pin placement. You have the choice of placing the RUP and RDN pins in the data-write group or in the same bank as the address and command pins.
There is no restriction on using ×16/×18 or ×32/×36 DQ/DQS groups that include the ×4 groups whose pins are being used as RUP and RDN pins, because there are enough extra pins that can be used as DQS pins.
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For ×8, ×16/×18, or ×32/×36 DQ/DQS groups whose members are used for RUP and RDN, you must assign DQS and DQ pins manually. The Quartus?II software might not be able to place DQS and DQ pins without manual pin assignments, resulting in a “no-fit”.
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface
This implementation combines ×16/×18 DQ/DQS groups to interface with a ×36 QDR II+/QDR II SRAM device. The ×36 read data bus uses two ×16/×18 groups, and the ×36 write data uses another two ×16/×18 or four ×8/×9 groups. The CQ/CQn signal traces are split on the board trace to connect to two pairs of CQ/CQn pins in the FPGA. This is the only connection on the board that you must change for this implementation. Other QDR II+/QDR II SRAM interface rules for Arria II devices also apply for this implementation.
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The ALTMEMPHY megafunction and UniPHY IP core do not use the QVLD signal, so you can leave the QVLD signal unconnected as in any QDR II+/QDR II SRAM interfaces in Arria II devices.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 7:External Memory Interfaces in ArriaII Devices
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface
fFor more information about the ALTMEMPHY megafunction and UniPHY IP core,
refer to the External Memory Interface Handbook.1
Use one side of the device with the ×36 mode emulation interface whenever possible, even though the ×36 group formed by a combination of DQ/DQS groups from the top and bottom I/O banks, or top/bottom I/O bank and left/right I/O banks is supported.
Rules to Combine Groups
Arria II Device Handbook Volume 1: Device Interfaces and IntegrationJune 2011Altera Corporation
Chapter 7:External Memory Interfaces in ArriaII Devices
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface
Table7–4 lists the possible combinations to use two ×16/×18 DQ/DQS groups to form a ×32/×36 group on Arria II devices lacking a native ×32/×36 DQ/DQS group.
Table7–4.Possible Group Combinations in Arria II DevicesDevice
Package
358-Pin Ultra FineLine BGA
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Device DensityEP2AGX45EP2AGX65EP2AGX45EP2AGX65EP2AGX95EP2AGX125EP2AGX45EP2AGX65EP2AGX95EP2AGX125EP2AGX190EP2AGX260EP2AGX95EP2AGX125EP2AGX190EP2AGX260EP2AGZ300EP2AGZ350EP2AGZ225EP2AGZ300 (4)EP2AGZ350 (4)EP2AGZ225EP2AGZ300 (4)EP2AGZ350 (4)
I/O Bank Combinations
4A and 7A (Top and Bottom I/O banks) (1)
572-Pin FineLine BGA
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7A and 8A (Top I/O banks)5A and 6A (Right I/O banks)3A and 4A (Bottom I/O banks)
ArriaIIGX
780-Pin FineLine BGA (2)
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7A and 8A (Top I/O banks)5A and 6A (Right I/O banks)3A and 4A (Bottom I/O banks)
1152-Pin FineLine BGA (2)
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7A and 8A (Top I/O banks)5A and 6A (Right I/O banks)3A and 4A (Bottom I/O banks)
Combine any two banks from each side of I/O banks3A and 4A, 7A and 8A (bottom and top I/O banks) (3)1A and 1C, 6A and 6C (left and right I/O banks)3A and 3B, 4A and 4B (bottom I/O banks)7A and 7B, 8A and 8B (top I/O banks)1A and 1C, 2A and 2C (left I/O banks)3A and 3B, 4A and 4B (bottom I/O banks)5A and 5C, 6A and 6C (right I/O banks)7A and 7B, 8A and 8B (top I/O banks)
780-Pin FineLine BGA
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ArriaIIGZ
1152-Pin FineLine BGA
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1517-Pin FineLine BGA
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Notes to Table7–4:
(1)Only one ×8/×9 group left in each of the remaining I/O banks. You can form only ?36 group write data with four ?8/?9 groups in these packages.(2)This device supports ?36 DQ/DQS groups on each side of I/O banks.
(3)Each side of the device in these packages has four remaining ×8/×9 groups. You can combine them for the write side (only) if you want to keep
the ×36 QDRII+/QDRII SRAM interface on one side of the device. In this case, you must change the Memory Interface Data Group defaultassignment from the default 18 to 9.(4)This device supports ×36 DQ/DQS groups on the top and bottom I/O banks natively.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 7:External Memory Interfaces in ArriaII Devices
Arria II External Memory Interface Features
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 7:External Memory Interfaces in ArriaII DevicesArria II External Memory Interface Features
Figure7–18 and Figure7–19 show how the DQS phase-shift circuitry is connected to the DQS/CQ and CQn pins in the device where memory interfaces are supported on the top, bottom, and right sides of the ArriaIIGX device and all sides of the ArriaIIGZ device.
Figure7–18.DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry for ArriaII GX Devices(Note1)
DLL ReferenceClock (2)DQS/CQPinCQnPinDQS/CQPinDQS LogicBlocksCQnPinΔtDQSPhase-ShiftCircuitry66ΔtΔtΔtto IOEto IOEto IOEto IOEDQS LogicBlocksto IOEΔtCQnPinto IOEΔtDQS/CQPinto IOEto IOEΔtCQnPinDQS/CQPinΔt66to IOEto IOEto IOEto IOEDQSPhase-ShiftCircuitryΔtΔtΔtΔtDLL ReferenceClock (2)CQnPinDQS/CQPinCQnPinDQS/CQPinNotes to Figure7–18:
(1)For possible reference input clock pins for each DLL, refer to “DLL” on page7–27.
(2)You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
Arria II Device Handbook Volume 1: Device Interfaces and Integration