loadingQ_n000930 : X_LUT2 generic map( INIT => X\ )
port map (
ADR0 => q_4_ibuf, ADR1 => q_5_ibuf, O => choice84 );
v55_2 : X_FF port map (
I => v55_n0000(2), RST => v55_2_GSR_OR, CE => n1198, CLK => clk_bufgp, O => v55(2), SET => GND );
v44_2 : X_FF port map (
I => v44_n0000(2), RST => v44_2_GSR_OR, CE => n1107, CLK => clk_bufgp, O => v44(2), SET => GND );
v33_2 : X_FF port map (
I => v33_n0000(2), RST => v33_2_GSR_OR, CE => n1063, CLK => clk_bufgp, O => v33(2), SET => GND );
v33_3 : X_FF port map (
I => v33_n0000(3), RST => v33_3_GSR_OR, CE => n1063, CLK => clk_bufgp, O => v33(3), SET => GND
29
);
v33_madd_n0000_inst_sum_1 : X_XOR2 port map (
I0 => v33_madd_n0000_inst_cy_0, I1 => v33_1_rt, O => v33_n0000(1) );
v33_aclr_inv1 : X_LUT2 generic map( INIT => X\ )
port map (
ADR0 => reset_ibuf, O => v33_0_n33, ADR1 => GND );
v33_0 : X_FF port map (
I => v33_madd_n0000_inst_lut2_0, RST => v33_0_GSR_OR, CE => n1063, CLK => clk_bufgp, O => v33(0), SET => GND );
v33_1 : X_FF port map (
I => v33_n0000(1), RST => v33_1_GSR_OR, CE => n1063, CLK => clk_bufgp, O => v33(1), SET => GND );
v44_3 : X_FF port map (
I => v44_n0000(3), RST => v44_3_GSR_OR, CE => n1107, CLK => clk_bufgp, O => v44(3), SET => GND );
v33_madd_n0000_inst_cy_1_1 : X_MUX2
30
port map (
IA => v2_0_obuf,
IB => v33_madd_n0000_inst_cy_0, SEL => v33_1_rt,
O => v33_madd_n0000_inst_cy_1 );
v5_0_obuf : X_BUF port map ( I => v55(0),
O => v5_0_obuf_GTS_TRI );
v44_0 : X_FF port map (
I => v44_madd_n0000_inst_lut2_0, RST => v44_0_GSR_OR, CE => n1107, CLK => clk_bufgp, O => v44(0), SET => GND );
v44_1 : X_FF port map (
I => v44_n0000(1), RST => v44_1_GSR_OR, CE => n1107, CLK => clk_bufgp, O => v44(1), SET => GND );
v55_3 : X_FF port map (
I => v55_n0000(3), RST => v55_3_GSR_OR, CE => n1198, CLK => clk_bufgp, O => v55(3), SET => GND );
v55_madd_n0000_inst_cy_2_2 : X_MUX2 port map (
IA => v2_0_obuf,
IB => v55_madd_n0000_inst_cy_1, SEL => v55_2_rt,
O => v55_madd_n0000_inst_cy_2
31
);
v33_madd_n0000_inst_cy_0_3 : X_MUX2 port map ( IA => n290, IB => v2_0_obuf,
SEL => v33_madd_n0000_inst_lut2_0, O => v33_madd_n0000_inst_cy_0 );
v55_0 : X_FF port map (
I => v55_madd_n0000_inst_lut2_0, RST => v55_0_GSR_OR, CE => n1198, CLK => clk_bufgp, O => v55(0), SET => GND );
v55_1 : X_FF port map (
I => v55_n0000(1), RST => v55_1_GSR_OR, CE => n1198, CLK => clk_bufgp, O => v55(1), SET => GND );
v55_madd_n0000_inst_sum_2 : X_XOR2 port map (
I0 => v55_madd_n0000_inst_cy_1, I1 => v55_2_rt, O => v55_n0000(2) );
xst_vcc : X_ONE port map ( O => n290 );
v55_madd_n0000_inst_cy_0_4 : X_MUX2 port map ( IA => n290, IB => v2_0_obuf,
SEL => v55_madd_n0000_inst_lut2_0, O => v55_madd_n0000_inst_cy_0 );
v5_2_obuf : X_BUF
32