loadingFast PLLs
StratixII devices contain up to eight fast PLLs with high-speed serial interfacing ability. Figure2–45 shows a diagram of the fast PLL.
Figure2–45.StratixII Device Fast PLL
Notes(1), (2), (3)
VCO Phase SelectionSelectable at each PLLOutput PortPost-ScaleCountersGlobal orregional clock (1)ClockSwitchoverCircuitry (4)PhaseFrequencyDetectordiffioclk0(2)÷c0load_en0(3)(5)ClockInput4÷nPFDChargePumpLoopFilterVCO÷k8÷c14÷c2load_en1(3)diffioclk1(2)Global clocksGlobal orregional clock (1)4÷c3÷m8Regional clocks8to DPA blockShaded Portions of thePLL are ReconfigurableNotes to Figure2–45:(1)
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES circuitry. StratixII devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.This signal is a differential I/O SERDES control signal.StratixII fast PLLs only support manual clock switchover.
If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
(2)(3)(4)(5)
f
See the PLLs in StratixII & StratixIIGX Devices chapter in volume2 of the StratixII Device Handbook or the StratixIIGX Device Handbook for more information on enhanced and fast PLLs. See “High-Speed
Differential I/O with DPA Support” on page2–96 for more information on high-speed differential I/O support.
The StratixII IOEs provide many features, including:
■■■■■■■■
I/O Structure
Dedicated differential and single-ended I/O buffers3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) supportOn-chip driver series terminationOn-chip parallel termination
On-chip termination for differential standardsProgrammable pull-up during configuration
Stratix II Device Handbook, Volume 1
StratixII Architecture
Figure2–55.Output TIming Diagram in DDR Mode
CLKA1A2A3A4From InternalRegistersB1B2B3B4DDR outputB1A1B2A2B3A3B4A4The StratixII IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock. This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, StratixII devices also have dedicated phase-shift circuitry for interfacing with external memory interfaces. StratixII devices support DDR and DDR2 SDRAM, QDR II SRAM, RLDRAMII, and SDR SDRAM memory interfaces. In every StratixII device, the I/O banks at the top (banks 3 and 4) and bottom (banks 7 and 8) of the device support DQ and DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table2–14 shows the number of DQ and DQS buses that are supported per device.
Table2–14.DQS & DQ Bus Mode Support(Part 1 of2)Device
EP2S15EP2S30EP2S60
Note(1)Number of ×8/×9 Groups
48484818
Package
484-pin FineLine BGA672-pin FineLine BGA484-pin FineLine BGA672-pin FineLine BGA484-pin FineLine BGA672-pin FineLine BGA1,020-pin FineLine BGA
Number of ×4Groups
81881881836
Number of Number of ×16/×18 Groups×32/×36 Groups
0404048
0000004
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Dedicated Circuitry with DPA Support
StratixII devices support source-synchronous interfacing with LVDS or HyperTransport signaling at up to 1 Gbps. StratixII devices can transmit or receive serial channels along with a low-speed or high-speed clock. The receiving device PLL multiplies the clock by an integer factor W=1 through 32. For example, a HyperTransport technology application where the data rate is 1,000 Mbps and the clock rate is 500 MHz would require that W be set to 2. The SERDES factor J determines the parallel data width to deserialize from receivers or to serialize for transmitters. The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the PLL clock-multiplication W value. A design using the dynamic phase aligner also supports all of these J factor values. For a J factor of 1, the StratixII device bypasses the SERDES block. For a J factor of 2, the StratixII device bypasses the SERDES block, and the DDR input and output registers are used in the IOE. Figure2–58 shows the block diagram of the StratixII transmitter channel.
Figure2–58.StratixII Transmitter Channel
Data from R4, R24, C4, ordirect link interconnect+–1010Up to 1 GbpsLocalInterconnectDedicatedTransmitterInterfacediffioclkrefclkFastPLLload_enRegional orglobal clockEach StratixII receiver channel features a DPA block for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel. In addition, you can dynamically switch between using the DPA block or bypassing the block via a control signal from the logic array. Figure2–59 shows the block diagram of the StratixII receiver channel.
Stratix II Device Handbook, Volume 1
StratixII Architecture
Figure2–59.StratixII Receiver Channel
Data to R4, R24, C4, ordirect link interconnectUp to 1 Gbps+–DQData RealignmentCircuitry10dataretimed_dataDPADPA_clkSynchronizerDedicatedReceiverInterfaceEight Phase Clocks8diffioclkrefclkFastPLLload_enRegional orglobal clockAn external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. In addition, eight phase-shifted clocks from the VCO can feed to the DPA circuitry.
f
For more information on the fast PLL, see the PLLs in StratixII &
StratixIIGX Devices chapter in volume 2 of the StratixII Device Handbook or the StratixIIGX Device Handbook.
The eight phase-shifted clocks from the fast PLL feed to the DPA block. The DPA block selects the closest phase to the center of the serial data eye to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of the channel-to-channel or clock-to-channel skew. The DPA block locks to a phase closest to the serial data phase. The phase-aligned DPA clock is used to write the data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment and SERDES circuitry. Since every channel utilizing the DPA block can have a different phase selected to sample the data, the synchronizer is needed to synchronize the data to the high-speed clock domain of the data realignment and the SERDES circuitry.
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Stratix II Device Handbook, Volume 1