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戈强宝 王春雷 廖乃全 201201902201 1101902318 201201902213
3-4 给出全减器的VHDL描述。 描述半减器的VHDL的程序如下:
library ieee;
use ieee.std_logic_1164.all; entity halfsub is
port(x,y:in std_logic;
diff,s_out:out std_logic); end entity halfsub;
architecture gl of halfsub is begin
process(x,y) begin
diff<= x xor y ;
s_out <= (not x) and y ; end process; end architecture gl; 半减器的仿真波形：
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描述或门的VHDL程序如下：
library ieee;
use ieee.std_logic_1164.all; entity or2a is
port(a,b:in std_logic;
sub_out:out std_logic); end entity or2a;
architecture gl of or2a is begin
sub_out <= a or b; end architecture gl;
描述全减器的VHDL的程序如下:
library ieee;
use ieee.std_logic_1164.all; entity fullsub is
port(x,y,sub_in:in std_logic;
diffr,sub_out:out std_logic); end entity fullsub;
architecture wgl of fullsub is signal net1,net2,net3:std_logic; component halfsub
port(x,y:in std_logic;
diff,s_out:out std_logic);
end component; component or2a
port(a,b:in std_logic;
sub_out:out std_logic);
end component; begin
u0:halfsub port map(x=>x,y=>y,diff=>net1,s_out=>net2);
u1:halfsub port map(x=>net1,y=>sub_in,diff=>diffr,s_out=>net3); u2:or2a port map(a=>net2,b=>net3,sub_out=>sub_out);
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end architecture wgl;
全减器的仿真波形：
3-5用VHDL设计一个3-8译码器。
library ieee;
use ieee.std_logic_1164.all; entity decoder38 is
port(a2,a1,a0:in std_logic;
y:out std_logic_vector(7 downto 0)); end entity decoder38;
architecture gl of decoder38 is
signal s: std_logic_vector(2 downto 0); begin
s<=a2&a1&a0;
process(a2,a1,a0) begin case (s) is
when \ when \ when \ when \ when \ when \ when \ when \ end case; end process;
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end architecture gl;
3-6 设计一个比较电路，当输入的8421BCD码大于5时输出1，否则
输出0
library ieee;
use ieee.std_logic_1164.all; entity comparator is
port(A,B,C,D:in std_logic; y:out std_logic); end entity comparator;
architecture gl of comparator is
signal s: std_logic_vector(3 downto 0); begin
s<=A&B&C&D;
process(A,B,C,D) begin case (s) is
when \ when \ when \ when \ when others=> y<= '0'; end case; end process;
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end architecture gl;
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