loading七段译码器 2-4线译码器 数据选择器 计数器
EWTH EWTL SNTH SNTL CP 东西及南北方向红绿灯时间及指示 CLK 分频器 图2-3：CPLD模块内部组成
以下为CPLD模块中的一些主要程序 1）红绿灯模块程序：
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jtd is port(clk:in bit;
ewr,ewy,ewg:out std_logic;
ewth,ewtl:out std_logic_vector(3 downto 0)); end jtd;
architecture a of jtd is
type rgyew is(yellow,green,red); --type rgysn is(yellow,green,red); begin process(clk)
variable aew:std_logic;
variable thew,tlew:std_logic_vector(3 downto 0); variable stateew:rgyew; begin
if clk'event and clk='1' then case stateew is
when green=>if aew='0' then
thew:=\tlew:=\aew:='1'; ewg<='1'; ewr<='0'; else
if not(thew=\if tlew=\
tlew:=\thew:=thew-1; else tlew:=tlew-1; end if; else
thew:=\ tlew:=\ aew:='0';
stateew:=yellow; end if; end if;
when red=>if aew='0' then
thew:=\tlew:=\aew:='1'; ewr<='1'; ewy<='0'; else
if not(thew=\
if tlew=\ tlew:=\
thew:=thew-1;
else
tlew:=tlew-1; end if;
else
thew:=\
tlew:=\ aew:='0';
stateew:=green;
end if; end if;
when yellow=>if aew='0' then
thew:=\tlew:=\aew:='1'; ewy<='1'; ewg<='0'; else
if not(thew=\
if tlew=\ tlew:=\
thew:=thew-1;
else
tlew:=tlew-1; end if;
else
thew:=\
tlew:=\ aew:='0'; stateew:=red;
end if; end if;
end case; end if; ewth<=thew; ewtl<=tlew; end process; end a;
2）分频器程序：
ENTITY clkdiv IS
PORT(clk:IN STD_LOGIC; clk_div12:OUT STD_LOGIC); END clk_div;
ARCHTECTURE rtl 0F clk_div IS
SIGNAL count:STD_LOGIC_VECTOR( 22 DOWNTO 0); SIGNAL clk_temp:STD_LOGIC; BEGIN
PROCESS(clk) BEGIN
IF(clk’event AND clk=’1’) THEN
IF(count=”10110111000110101111111”) THEN count<=(OTHERS=>’0’); clk_temp<=NOT clk_temp; ELSE
count<=count+1; END IF; END IF; END PROCESS; clk_div12<=clk_temp; END rtl； 3）七段译码器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY sevenv IS
PORT(d:IN INTEGER RANGE 0 TO 15; S:OUT STD _LOGIC_VETOR(0 DOWNTO 6)); END sevenv;
ARCHTECTURE a OF sevenv IS