loading附录：实验程序清单
module dianzhen row<=row2; //列(clk50mhz,row,sel0,sel1,sel2,sel3,line); 扫描 input clk50mhz; line<=line2;
end //实验箱提供50MHz时钟信号
output sel0,sel1,sel2,sel3; Endmodule
//设置引脚选通点阵
output reg [15:0] row; 行扫描
//列
output reg [3:0] line; //行 wire [15:0] row1,row2; wire [3:0] line1,line2; reg [24:0] cnt=0; //1Hz计数子 reg [5:0] cnt1=0; //16s计数子 assign sel0=1'b0; assign sel1=1'b1; assign sel2=1'b0; assign sel3=1'b0; always@(posedge clk50mhz) begin if(cnt>=25'd50000000) begin cnt<=25'b0; //1Hz计时器
cnt1<=cnt1+1; //16s计时器
end else cnt<=cnt+1; end hangsaomiao u1(.clk50mhz(clk50mhz),.row(row1),.line(line1)); liesaomiao u2(.clk50mhz(clk50mhz),.row(row2),.line(line2)); always@(*) if(cnt1<=5'd31) begin row<=row1; //行
扫描
line<=line1; end else begin module hangsaomiao(clk50mhz,line,row); input clk50mhz; //实验箱输入50MHz时钟信号 output reg [15:0] row; //列 output reg [3:0] line; //行 reg [24:0] cnt1,cnt2; //计数子 reg clkrow,clkline; //列脉冲、行脉冲 always@(posedge clk50mhz) begin if(cnt1>=25'd50000000) begin cnt1<=25'b0; clkrow=~clkrow; //1s列脉冲
end else cnt1<=cnt1+1; end always@(posedge clk50mhz) begin if(cnt2>=25'd500) begin cnt2<=25'b0; clkline=~clkline; //100KHz行脉冲 end else
cnt2<=cnt2+1; end always@(posedge clkline) begin case(line) 4'd0:line<=4'd1; //
高速行扫描 4'd1:line<=4'd2; 4'd2:line<=4'd3; 4'd3:line<=4'd4; 4'd4:line<=4'd5; 4'd5:line<=4'd6; 4'd6:line<=4'd7; 4'd7:line<=4'd8; 4'd8:line<=4'd9; 4'd9:line<=4'd10; 4'd10:line<=4'd11; 4'd11:line<=4'd12; 4'd12:line<=4'd13; 4'd13:line<=4'd14; 4'd14:line<=4'd15; 4'd15:line<=4'd0; default:line<=4'd0; endcase end
always@(posedge
//时间间隔为1s的列扫描 begin case(row) 16'b0000000000000001: row<=16'b0000000000000010; 16'b0000000000000010: row<=16'b0000000000000100; 16'b0000000000000100: row<=16'b0000000000001000; 16'b0000000000001000: row<=16'b0000000000010000; 16'b0000000000010000: row<=16'b0000000000100000; 16'b0000000000100000: row<=16'b0000000001000000; 16'b0000000001000000: row<=16'b0000000010000000; 16'b0000000010000000: row<=16'b0000000100000000; 16'b0000000100000000: row<=16'b0000001000000000; 16'b0000001000000000: row<=16'b0000010000000000; 16'b0000010000000000: row<=16'b0000100000000000; 16'b0000100000000000: row<=16'b0001000000000000;
16'b0001000000000000: row<=16'b0010000000000000; 16'b0010000000000000: row<=16'b0100000000000000; 16'b0100000000000000: row<=16'b1000000000000000; 16'b1000000000000000: row<=16'b0000000000000001; default : row<=16'b0000000000000001; endcase end endmodule
列扫描
module liesaomiao(clk50mhz,row,line); input clk50mhz; //实验箱输入50MHz时钟信号
clkrow) output reg [15:0] row; //行 output reg [3:0] line; //列 reg [24:0] cnt; //计数子
reg clk; always@(posedge clk50mhz) begin if(cnt>=25'd50000000) begin cnt<=25'b0; clk=~clk; //1s end else cnt<=cnt+1; end always @ (posedge clk) //列扫描 begin case(line) 4'h0:begin
row=16'b1111111111111111;line<=4'h1;end 4'h1:begin
row=16'b1111111111111111;line<=4'h2;end 4'h2:begin
row=16'b1111111111111111;line<=4'h3;end
4'h3:begin
row=16'b1111111111111111;line<=4'h4;end 4'h4:begin
row=16'b1111111111111111;line<=4'h5;end 4'h5:begin
row=16'b1111111111111111;line<=4'h6;end 4'h6:begin
row=16'b1111111111111111;line<=4'h7;end 4'h7:begin
row=16'b1111111111111111;line<=4'h8;end 4'h8:begin
row=16'b1111111111111111;line<=4'h9;end 4'h9:begin
row=16'b1111111111111111;line<=4'ha;end 4'ha:begin
row=16'b1111111111111111;line<=4'hb;end 4'hb:begin
row=16'b1111111111111111;line<=4'hc;end 4'hc:begin
row=16'b1111111111111111;line<=4'hd;end 4'hd:begin
row=16'b1111111111111111;line<=4'he;end 4'he:begin
row=16'b1111111111111111;line<=4'hf;end 4'hf:begin
row=16'b1111111111111111;line<=4'h0;end default:line<=4'h0; endcase end
endmodule