loadingTable6-10 defines the TX buffering and phase-alignment attributes.
Table 6-10:
TX Buffering and Phase-Alignment Attributes
Type
Description
This shared attribute activates the built-in 5x digital oversampling circuits in both GTX_DUAL transceivers. Oversampling is supported between 1/10th of the lower border of the shared PMA PLL operating range and 4/10th of the upper border of the shared PMA PLL operating range. For data rates that need a PLL clock without oversampling that is below one-half of the lower border of the shared PMA PLL, oversampling is mandatory to ensure that the shared PMA PLL operates in its frequency range.
TRUE: Built-in 5x digital oversampling enabled for both GTX transceivers on the tile
FALSE: Digital oversampling disabled
See “Oversampling,” page 185 for more details about 5x digital oversampling.
PLL_TXDIVSEL_OUT_0PLL_TXDIVSEL_OUT_1PMA_TX_CFG_0PMA_TX_CFG_1TX_BUFFER_USE_0TX_BUFFER_USE_1
Divides the PLL clock to produce a high-speed TX clock. Because both edges of the clock are used, the divided clock must run at one-half the desired TX line rate. Available divider settings are 1, 2, and 4. Each GTX transceiver has a separate PLL_TXDIVSEL_OUT. See “Parallel In to Serial Out,” page 149.TX channel specific settings. The default value is 20'h80082.This attribute must be set to TRUE when the TX buffer is used.
Boolean
TRUE: Use the TX buffer.
FALSE: Bypass the TX buffer. The phase-alignment circuit must be used when TX_BUFFER_USE is FALSE.(1)
Selects the clock used to drive the clock domain in the PCS following the TX buffer. When using the TX buffer, this attribute is set to TXOUT.
String
The attribute must be set as follows:
TXOUT: Use when TX_BUFFER_USE = TRUETXUSR: Use when TX_BUFFER_USE = FALSE(1)
Controls inverters that optimize the clock paths within the GTX transceiver for different modes of operation. When using the TX buffer, this attribute must be set to 3'b011.
The attribute must be set as follows:
011: Use when TX_BUFFER_USE=TRUE111: Use when TX_BUFFER_USE=FALSE(1)
Notes:
1.Bypassing the TX buffer is an advanced feature and is not recommended for normal operation. TX buffer bypass operation can beguaranteed only under certain system-level conditions and data rates.
Attribute
OVERSAMPLE_MODEBoolean
Integer
20-bit Hex
TX_XCLK_SEL0TX_XCLK_SEL1
TXRX_INVERT0TXRX_INVERT1
3-bit Binary
Description
Using the TX Buffer
To use the TX buffer to resolve phase differences between the domains, TX_BUFFER_USE must be set to TRUE. The buffer should be reset whenever TXBUFSTATUS indicates an overflow or an underflow. The buffer can be reset using GTXRESET (see “Reset,” page 101)
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
TX Out-of-Band/Beacon Signaling
TX Out-of-Band/Beacon Signaling
Overview
Each GTX transceiver provides support for generating the Out-of-Band (OOB) sequences described in the Serial ATA (SATA) specification and beaconing described in the PCI
Express specification. See AppendixB, “OOB/Beacon Signaling,” for an overview of OOB signaling and how it is used in these protocols.
GTX_DUAL support for SATA OOB signaling consists of the analog circuitry required to encode the OOB signal state and state machines to format bursts of OOB signals for SATA COM sequences (COMRESET, COMWAKE, and COMINIT). Each GTX transceiver also supports SATA auto-negotiation by allowing the timing of the COM sequences to be changed based on the divider settings used for the TX line rate.
GTX_DUAL supports beaconing as described in the PHY Interface for the PCI Express (PIPE) Specification. The format of the beacon sequence is controlled by the FPGA logic.
Ports and Attributes
Table6-20 describes the ports that control OOB/beacon signaling.
Table 6-20:
TX OOB/Beacon Signaling Ports
Direction
Domain
Description
The decoding of RXSTATUS[2:0] depends on the setting of RX_STATUS_FMT:
?When RX_STATUS_FMT = PCIE:
RXSTATUS0[2:0]RXSTATUS1[2:0]
Out
RXUSRCLK2
RXSTATUS is not used for PCIe TXELECIDLE?When RX_STATUS_FMT = SATA:
RXSTATUS[0]: TXCOMSTART operation completeRXSTATUS[1]: COMWAKE signal received
RXSTATUS[2]: COMRESET/COMINIT signal received
TXCOMSTART0TXCOMSTART1TXCOMTYPE0TXCOMTYPE1TXELECIDLE0TXELECIDLE1
TXPOWERDOWN0[1:0]TXPOWERDOWN1[1:0]
In
TXUSRCLK2
Initiates the transmission of the COM* sequence selected by TXCOMTYPE (SATA only).
Selects the type of COM signal to send (SATA only):
In
TXUSRCLK2
0: COMRESET/COMINIT1: COMWAKE
In
TXUSRCLK2
When in the P2 power state, this signal controls whether an
electrical idle or a beacon indication is driven out onto the TX pair.Powers down the TX lanes. When in PCIe mode, the GTX_DUAL tile must be in the P2 power state (TXPOWERDOWN = 11) to generate beacon signaling. Use TXPOWERDOWN = 00 for SATA OOB signaling.
Port
InTXUSRCLK2
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 6:GTX Transmitter (TX)
Table6-21 defines the OOB/beacon signaling attributes.Table 6-21:
TX OOB/Beacon Signaling Attributes
Type4-bit Binary
Description
Number of bursts in a COM sequence.
Tie to FALSE. When FALSE, PLL_SATA allows TX SATA operations to work at the SATA Generation 1 (1.5Gb/s) or SATA Generation 2 (3Gb/s) rate.Sets the divider for the TX line rate for the
individual GTX transceiver. Can be set to 1, 2, or 4.
Attribute
COM_BURST_VAL_0COM_BURST_VAL_1PLL_SATA_0PLL_SATA_1
PLL_TXDIVSEL_OUT_0PLL_TXDIVSEL_OUT_1
Boolean
Integer
Description
The GTX_DUAL tile supports two signaling modes: one for SATA operations and one for PCI Express operations. The use of these two mechanisms is mutually exclusive.
Beacon Signaling for PCI Express Operations
Beacon signaling for PCI Express operations is performed when the GTX_DUAL tile is in the P2 power state. Transmission of a beacon is initiated by the deassertion of
TXELECIDLE, as shown in Figure6-26. FPGA control logic controls beacon timing by the sequencing of TXELECIDLE.
X-Ref Target - Figure 6-26TXPOWERDOWN[1:0]11TXELECIDLETXN/TXPValid Beacon SignalingUG198_c6_26_101207Figure 6-26:Beacon Generation for PCI Express Operations
OOB Signaling for SATA Operations
OOB signaling for SATA operation is initiated through the use of the TXELECIDLE, TXCOMSTART, and TXCOMTYPE ports. When TXELECIDLE is held High, assertion of TXCOMSTART for one TXUSRCLK2 cycle initiates the transmission of a COM sequence. The type of COM sequence generated is controlled by the TXCOMTYPE port as shown in Table6-20.
The number of bursts in the COM sequence is controlled by the COM_BURST_VAL
attribute. The timing of the COM sequences transmitted is correct as long as the PLL clock (see “Shared PMA PLL,” page 86) is set to 1.5GHz, and PLL_TXDIVSEL_OUT for each channel is set to either 1 (for a 3.0 Gb/s SATA Generation2 rate) or 2 (for a 1.5 Gb/s SATA Generation1 rate).
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 7:GTX Receiver (RX)
10.“Configurable Loss-of-Sync State Machine,” page 19711.“Configurable 8B/10B Decoder,” page 200
12.“Configurable RX Elastic Buffer and Phase Alignment,” page 20313.“Configurable Clock Correction,” page 211
14.“Configurable Channel Bonding (Lane Deskew),” page 21815.“RX Gearbox,” page 23116.“FPGA RX Interface,” page 236
RX Termination and Equalization
Overview
The first stage of the RX datapath in each GTX transceiver is the RX current mode logic (CML)receiver. This block determines the value of the incoming high-speed differentialsignal.
At high speeds, error-free data reception requires good signal integrity. The CML receiver includes circuits to allow the termination of the channel to be optimized for the best possible signal integrity.
The receiver also features an RX equalization circuit that allows it to compensate for high-frequency losses in the channel, improving the quality of the received signal. This circuit can be tuned to meet the specific requirements of the physical channel used in the design.
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
RX Termination and Equalization
Table7-2 describes the attributes and settings regarding termination for both receivers of the GTX_DUAL tile.
Table 7-2:
RX Termination and Equalization Attributes
Type
Description
Bypasses the built-in AC coupling in the receiver. Use this attribute when DC coupling is required. The default for this attribute is FALSE for PCI Express designs. For all other protocols, the default setting is TRUE.
AC_CAP_DIS_0AC_CAP_DIS_1
Boolean
TRUE: Built-in AC coupling capacitors are bypassed. DC coupling to the receiver is possible.
FALSE: Built-in AC coupling capacitors are enabled.
See Chapter10, “GTX-to-Board Interface,” for details about when it is appropriate to add an additional external AC coupling capacitor based on data rate or protocol.
CM_TRIM_0CM_TRIM_1
2-bit Binary
Adjusts the input common mode levels. These levels are automatically set in the RocketIO? GTX Transceiver Wizard.
Activates the Ground reference for the receiver termination network. The default for this attribute is TRUE for PCI Express designs. For all other protocols, the default setting is FALSE.
Boolean
TRUE: Ground reference for receiver termination activated.FALSE: Ground reference for receiver termination disabled.See Table7-4, page165 for valid combinations of RX termination attributes. Must be set to TRUE for PCI Express designs.
Activates MGTAVTTRX reference for receiver termination network. The default for this attribute is FALSE for PCI Express designs. For all other protocols, the default setting is TRUE. Set to FALSE when using AC coupling.
TRUE: MGTAVTTRX reference for receiver termination activated.FALSE: MGTAVTTRX reference for receiver termination disabled.See Table7-4, page165 for valid combinations of RX termination attributes.
Selects the termination impedance for the TX driver and RX CML receiver.
TERMINATION_IMP_0TERMINATION_IMP_1
Integer
See Chapter10, “GTX-to-Board Interface,” for details on calibration of impedance values.
Always set to 50 to select 50Ω termination impedance. The RocketIO GTX Transceiver Wizard automatically sets this parameter to 50.
Attribute
RCV_TERM_GND_0RCV_TERM_GND_1
RCV_TERM_VTTRX_0RCV_TERM_VTTRX_1
Boolean
Description
The GTX_DUAL receivers are connected via differential pad pairs RXN and RXP to the transmission line on the board. The receiver includes four main features for optimizing signal integrity:????
Optional Built-in AC CouplingConfigurable Termination ImpedanceConfigurable Termination Voltage
Optional 4-Mode Active Linear Equalization
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009