loadingSymbol
IDELAYCTRLTIDELAYCTRLCO_RDYFIDELAYCTRL_REFTIDELAYCTRL_RPWIODELAY
TIDELAYRESOLUTION
Description
Speed Grade-2I3.00200.00±1050.00
-1I3.00200.00±1050.00
-1M3.00200.00±1050.00
Units
Reset to Ready for IDELAYCTRLREFCLK frequencyMinimum Reset pulse width
μsMHzMHzns
IDELAYCTRL_REF_PRECISIONREFCLK precision
IODELAY Chain Delay Resolution
Pattern dependent period jitter in delay chain for clock pattern
Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)
Maximum frequency of CLK input to IODELAYCE pin Setup/Hold with respect to CKINC pin Setup/Hold with respect to CKRST pin Setup/Hold with respect to CK
TSCONTROL delay to MUXE/MUXF switching and through IODELAY
Propagation delay through IODELAYPropagation delay through IODELAY
0
1/(64xFREFx1e6)(1)
0±52500.42–0.060.240.060.33–0.12Note3Note3Note3
0±52500.42–0.060.240.060.33–0.12Note3Note3Note3
psNote2Note2MHznsnsns
TIDELAYPAT_JIT
±52500.34–0.060.200.040.28–0.12Note3Note3Note3
TIODELAY_CLK_MAXTIODCCK_CE/ TIODCKC_CETIODCK_INC/ TIODCKC_INCTIODCK_RST/ TIODCKC_RSTTIODDO_TTIODDO_IDATAINTIODDO_ODATAIN
Notes:
1.Average Tap Delay at 200MHz=78ps.
2.Units in ps, peak-to-peak per tap, in High Performance mode.
3.Delay depends on IODELAY tap setting. See TRACE report for actual values.
CLB Switching Characteristics
Table 65:CLB Switching Characteristics
SymbolCombinatorial DelaysTILO
An–Dn LUT address to A
An–Dn LUT address to AMUX/CMUXAn–Dn LUT address to BMUX_A
TITOTAXATAXBTAXCTAXDTBXB
An–Dn inputs to A–D Q outputsAX inputs to AMUX outputAX inputs to BMUX outputAX inputs to CMUX outputAX inputs to DMUX outputBX inputs to BMUX output
0.090.220.350.770.440.520.360.620.41
0.100.250.400.900.530.610.420.730.48
0.100.250.400.900.530.610.420.730.48
ns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Max
Description
Speed Grade
-2I
-1I
-1M
Units
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 74:PLL Specification
Symbol
FINMAXFINMINFINJITTERFINDUTY
Description
Maximum Input Clock FrequencyMinimum Input Clock FrequencyMaximum Input Clock Period JitterAllowable Input Duty Cycle: 19—49MHzAllowable Input Duty Cycle: 50—199MHzAllowable Input Duty Cycle: 200—399MHzAllowable Input Duty Cycle: 400—499MHzAllowable Input Duty Cycle: >500MHz
Speed Grade-2I71019
-1I6451925/7530/7035/6540/6045/55
-1M64519
UnitsMHzMHz%%%%%
<20% of clock input period or 1ns Max
FVCOMINFVCOMAXFBANDWIDTHTSTAPHAOFFSETTOUTJITTERTOUTDUTYTLOCKMAXFOUTMAX
Minimum PLL VCO FrequencyMaximum PLL VCO FrequencyLow PLL Bandwidth at Typical(1)High PLL Bandwidth at Typical(1)Static Phase Offset of the PLL OutputsPLL Output Jitter(2)
PLL Output Clock Duty Cycle Precision(3)PLL Maximum Lock Time(4)
PLL Maximum Output Frequency for LX30T, LX85, LX110, LX110T, SX50T, and FX70T(I) devices
PLL Maximum Output Frequency for LX155T, FX70T(M), and FX100T devices
PLL Maximum Output Frequency for FX130T devicesPLL Maximum Output Frequency for LX220T, LX330T, SX95T, SX240T, and FX200T devices
400120014120±2001006676005005003.125550019
400100014120Note 1±2001006005504504503.125545019
400100014120±200100N/A550N/AN/A3.125545019
MHzMHzMHzMHzpspsμsMHzMHzMHzMHzMHznsMHzMHz
FOUTMINTEXTFDVARRSTMINPULSEFPFDMAXFPFDMINTFBDELAYNotes:
1.2.3.4.5.
PLL Minimum Output Frequency(5)External Clock Feedback VariationMinimum Reset Pulse Width
Maximum Frequency at the Phase Frequency DetectorMinimum Frequency at the Phase Frequency DetectorMaximum Delay in the Feedback Path
<20% of clock input period or 1ns Max
3ns Max or one CLKIN cycle
The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.Values for this parameter are available in the Architecture Wizard.Includes global clock buffer.
The LOCK signal must be sampled after TLOCKMAX. The LOCK signal is invalid after configuration or reset until the TLOCKMAX time hasexpired.
Calculated as FVCO/128 assuming output duty cycle is 50%.
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DCM Switching Characteristics
Table 76:Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Symbol
Outputs Clocks (Low Frequency Mode)F1XLFMSMINF1XLFMSMAXF2XLFMSMINF2XLFMSMAXFDVLFMSMINFDVLFMSMAXFFXLFMSMINFFXLFMSMAX
CLKFX, CLKFX180CLKDV(5)
CLK2X, CLK2X180
CLK0, CLK90, CLK180, CLK270
32.00135.0064.00270.002.090.0032.00160.00
CLKIN (using DLL outputs)(1)(3)(4)CLKIN (using DFS outputs only)(2)(3)(4)PSCLK
32.00120.0064.00240.002.080.0032.00140.00
32.00120.0064.00240.002.080.0032.00140.00
MHzMHzMHzMHzMHzMHzMHzMHz
Description
Speed Grade-2I
-1I
-1M
Units
Input Clocks (Low Frequency Mode)FDLLLFMSMINFDLLLFMSMAXFCLKINLFFXMSMINFCLKINLFFXMSMAXFPSCLKLFMSMINFPSCLKLFMSMAX
32.00135.001.00160.001.00500.00
32.00120.001.00140.001.00450.00
32.00120.001.00140.001.00450.00
MHzMHzMHzMHzKHzMHz
Outputs Clocks (High Frequency Mode)F1XHFMSMINF1XHFMSMAXF2XHFMSMINF2XHFMSMAXFDVHFMSMINFDVHFMSMAXFFXHFMSMINFFXHFMSMAX
CLKFX, CLKFX180(5)CLKDV(5)
CLK2X, CLK2X180
CLK0, CLK90, CLK180, CLK270
120.00500.00240.00500.007.5333.34140.00375.00
CLKIN (using DLL outputs)(1)(3)(4)
CLKIN (using DFS outputs only)(2)(3)(4)(5)PSCLK
120.00450.00240.00450.007.5300.00140.00350.00
120.00450.00240.00450.007.5300.00140.00350.00
MHzMHzMHzMHzMHzMHzMHzMHz
Input Clocks (High Frequency Mode)FDLLHFMSMINFDLLHFMSMAXFCLKINHFFXMSMINFCLKINHFFXMSMAXFPSCLKHFMSMINFPSCLKHFMSMAXNotes:
1.2.3.4.5.
DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum inputfrequency.
When using a CLKIN frequency > 400MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55to 55/45).
Only available for I-temperature conditions.
120.00500.0025.00375.001.00500.00
120.00450.0025.00350.001.00450.00
120.00450.0025.00350.001.00450.00
MHzMHzMHzMHzKHzMHz
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011Product Specification