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管脚序号 管脚名称 扩展功能 新定义 1 PE2 TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT TRACED0/FSMC_A19 / EVENTOUT TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT EVENTOUT EVENTOUT EVENTOUT 2 3 4 PE3 PE4 PE5 5 PE6 6 7 8 9 VBAT PC13 PC14-OSC32_IN (PC14) PC15- OSC32_OUT (PC15) VSS VDD PH0-OSC_IN (PH0) PH1-OSC_OUT (PH1) NRST PC0 PC1 PC2 10 11 12 13 14 15 16 17 EVENTOUT EVENTOUT OTG_HS_ULPI_STP/ EVENTOUT ETH_MDC/ EVENTOUT SPI2_MISO / OTG_HS_ULPI_DIR / TH_MII_TXD2 /I2S2ext_SD/ EVENTOUT SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT 18 PC3 19 20 21 ;.
VDD VSSA VREF+ ..
22 23 VDDA PA0-WKUP (PA0) USART2_CTS/ UART4_TX/ ETH_MII_CRS / TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ EVENTOUT USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIMM2_CH2/ EVENTOUT USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CHIN/ EVENTOUT SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN/ EVENTOUT SPI1_MOSI/ TIM8_CH1N / TIM14_CH1/TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / RMII_CRS_DV/ EVENTOUT ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT 24 PA1 25 PA2 26 PA3 27 28 29 VSS VDD PA4 30 PA5 31 PA6 32 PA7 33 PC4 ;.
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34 PC5 ETH_RMII_RX_D1 / ETH_MII_RX_D1/ EVENTOUT TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / OTG_HS_INTN / TIM1_CH3N/ EVENTOUT EVENTOUT FSMC_D4/TIM1_ETR/ EVENTOUT FSMC_D5/ TIM1_CH1N/ EVENTOUT FSMC_D6/TIM1_CH1/ EVENTOUT FSMC_D7/TIM1_CH2N/ EVENTOUT FSMC_D8 / TIM1_CH2 / EVENTOUT FSMC_D9/TIM1_CH3N/ EVENTOUT FSMC_D10/TIM1_CH3/ EVENTOUT FSMC_D11/TIM1_CH4/ EVENTOUT FSMC_D12/TIM1_BKIN/ EVENTOUT SPI2_SCK / I2S2_CK / I2C2_SCL/ USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT SPI2_NSS / I2S2_WS / 35 PB0 36 PB1 37 38 39 40 41 42 43 44 45 46 47 PB2-BOOT1 (PB2) PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 48 PB11 49 50 51 ;.
VCAP_1 VDD PB12 ..
I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT 52 PB13 SPI2_SCK / I2S2_CK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/ USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT SPI2_MOSI / I2S2_SD/ TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT FSMC_D13 / USART3_TX/ EVENTOUT FSMC_D14 / USART3_RX/ EVENTOUT FSMC_D15 / USART3_CK/ EVENTOUT FSMC_CLE / FSMC_A16/USART3_CTS/ EVENTOUT FSMC_ALE/ FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT FSMC_A18/TIM4_CH2/ EVENTOUT FSMC_D0/TIM4_CH3/ EVENTOUT/ EVENTOUT FSMC_D1/TIM4_CH4/ EVENTOUT I2S2_MCK / 53 PB14 54 PB15 55 56 57 58 PD8 PD9 PD10 PD11 59 PD12 60 61 62 63 ;.
PD13 PD14 PD15 PC6