loading
output s1, s0;
assign s1 = a & b; assign s0 = a ^ b;
endmodule ②测试模块 `timescale 1ns/1ps module tb_shared; reg a_test; reg b_test; reg c_test; reg d_test; reg m_test; wire s1_test; wire s0_test; initial m_test=0;
always #80 m_test=~m_test; initial
begin a_test=0; b_test=0; c_test=0; d_test=0; #20 a_test=0; b_test=1; c_test=0; d_test=0; #20 a_test=1; b_test=0; c_test=0; d_test=0; #20 a_test=1; b_test=1; c_test=0;
d_test=0; #20 a_test=0; b_test=0; c_test=0; d_test=0; #20 a_test=0; b_test=0; c_test=0; d_test=1; #20 a_test=0; b_test=0; c_test=1; d_test=0; #20 a_test=0;
b_test=0; c_test=1; d_test=1; end shared
UUT_shared(.a(a_test),.b(b_test),.c(c_test),.d(d_test),.m(m_test),.s1(s1_test),.s0(s0_test));
endmodule
③仿真后的波形截图
④对波形的分析
本例是由两个二选一多路选择器和一个两位二进制数加法器构成的电路。分析上图波形，当m信号为0时，加法器计算a和b的和；当m信号为1时，加法器计算c和d的和。所以