FPGA可编程逻辑器件芯片XCZU3EG-2SFVA625I中文规格书 - 图文

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Packaging Overview

Summary

This chapter covers the following topics:???

Introduction

Device/Package Combinations and Maximum I/OsPin Definitions

Introduction

This section describes the pinouts for Virtex?-5 devices in the 1.00mm pitch flip-chip fine-pitch BGA packages.

Virtex-5 devices are offered exclusively in high performance flip-chip BGA packages that are optimally designed for improved signal integrity and jitter. Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of Power and GND pins.

All of the devices supported in a particular package are pinout compatible and are listed in the same table (one table per package). Pins that are not available for the smaller devices are listed in the “No Connects” column of each table.

For Virtex-5Q devices, the EF package is offered. The only difference between an EF and an FF package is that the discrete substrate capacitors on the EF package are coated with epoxy. The coating is comprised of an undercoat epoxy that is dispensed under the

capacitors and an overcoat epoxy that is dispensed over the top of the capacitors. All other package construction characteristics of the EF matches that of the FF package. The EF package changes are noted in Chapter4, “Mechanical Drawings.”

Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/O standards (see UG190: Virtex-5 FPGA User Guide). Global pins, including JTAG, configuration, and power/ground pins, are listed at the end of each table. Table1-7 provides definitions for all pin types.

For information on package electrical characteristics and how the characteristics are measured, refer to UG112: Device Package User Guide found on the Xilinx website.For the latest Virtex-5 FPGA pinout information, check the Xilinx website for any updates to this document.

Virtex-5 FPGA Packaging and Pinout Specification

Chapter 1:Packaging Overview

Device/Package Combinations and Maximum I/Os

Table1-1 shows the maximum number of user I/Os possible in Virtex-5 FPGA flip-chip packages. FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).

Table 1-1:

Flip-Chip Packages

Packages

FF3241.0019 x 19220

FF6651.0027 x 27360

FF6761.0027 x 27440

FF1136FF11531.0035 x 35640

1.0035 x 35800

FF11561.0035 x 35360

FF17381.0042.5 x 42.5960

FF17591.0042.5 x 42.5680

FF17601.0042.5 x 42.51200

Package

SpecificationsFF323Pitch(mm)Size(mm)Maximum I/Os

1.0019 x 19172

The number of I/Os per package includes all user I/Os except the 19 pins listed in Table1-2.

Table 1-2:Virtex-5 FPGA I/O Pinsin the Dedicated Configuration Bank (Bank0)DXPDXNVBATTPROGRAM_B

HSWAPEND_INDONECCLK_0

INIT_B_0CS_B_0RDWR_B_0TCK_0

M0_0M1_0M2_0TMS

TDI

D_OUT_BUSYTDO_0

Virtex-5 FPGA Packaging and Pinout Specification

Chapter 2:Pinout Tables

Table 2-10:

Bank292929292929303030303030303030303030303030303030303030303030303030

FF1760 Package—LX110, LX155, LX220, and LX330 (Continued)

Pin Description

Pin Number

BB32BB31BA30BA31AY30AW31AV1AW1AW2AY2BA1BA2AY3AW3BB2BB3AY5AW5AY4BA4BA5BB4BB7BA7AW7AW6BB6BA6AY7AW8BB8BA9AY10

No Connect (NC)

IO_L17P_29 IO_L17N_29 IO_L18P_29 IO_L18N_29 IO_L19P_29 IO_L19N_29 IO_L0P_30 IO_L0N_30 IO_L1P_30 IO_L1N_30 IO_L2P_30 IO_L2N_30 IO_L3P_30 IO_L3N_30 IO_L4P_30 IO_L4N_VREF_30 IO_L5P_30 IO_L5N_30 IO_L6P_30 IO_L6N_30 IO_L7P_30 IO_L7N_30 IO_L8P_CC_30 IO_L8N_CC_30(2)IO_L9P_CC_30 IO_L9N_CC_30(2)IO_L10P_CC_30 IO_L10N_CC_30(2)IO_L11P_CC_30 IO_L11N_CC_30(2)IO_L12P_VRN_30 IO_L12N_VRP_30 IO_L13P_30

LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220LX110, LX155, LX220

Virtex-5 FPGA Packaging and Pinout Specification

FF1760 Package—LX110, LX155, LX220, and LX330

Table 2-10:

Bank303030303030303030303030303131313131313131313131313131313131313131

FF1760 Package—LX110, LX155, LX220, and LX330 (Continued)

Pin Description

Pin NumberAW10BB9BA10AY8AY9AW11AW12BA12BB12BB11BA11AY13AY12E14D15E15F14D16D17F16F15F17E17E20F20D18E18E19F19D22D23D21D20

No Connect (NC)

IO_L13N_30 IO_L14P_30 IO_L14N_VREF_30 IO_L15P_30 IO_L15N_30 IO_L16P_30 IO_L16N_30 IO_L17P_30 IO_L17N_30 IO_L18P_30 IO_L18N_30 IO_L19P_30 IO_L19N_30 IO_L0P_31 IO_L0N_31 IO_L1P_31 IO_L1N_31 IO_L2P_31 IO_L2N_31 IO_L3P_31 IO_L3N_31 IO_L4P_31 IO_L4N_VREF_31 IO_L5P_31 IO_L5N_31 IO_L6P_31 IO_L6N_31 IO_L7P_31 IO_L7N_31 IO_L8P_CC_31 IO_L8N_CC_31(2)IO_L9P_CC_31 IO_L9N_CC_31(2)

Virtex-5 FPGA Packaging and Pinout Specification

FF324 Package—LX30 and LX50

X-Ref Target - Figure 3-31ABCDEFGHJKLMNPRTUV123456789101112131415161718SSSLYKCDNAIOMSSSJABCDEFGHJKL1MN02PRURRBTHPUV11121314151617182345678910User I/O PinsMulti-Function PinsIO_LXXY_#VREFVRNVRPP_GCN_GCCCD0 - D31A0 - A25SMDedicated PinsPPROGRAM_BCCCLKBCS_BND_INDDONEHHSWAPENYINITURDWR_BKTCKITDIOther PinsGNDRRSVDVBATTVCCAUXVCCINTVCCOnNO CONNECTAD_OUT_BUSYOTDOMTMSJDXP210M2, M1, M0LDXNSAVDD_0, AVSS_0, VP_0,VN_0, VREFP_0, VREFN_0ug195_c3_01_012907Figure 3-3:

X-Ref Target - Figure 3-4FF324 Package—LX30 and LX50 Pinout Diagram

246810121416181ABCDEFGHJKLMNPRTUV357911131517121212121212121212121212121212121212121212121818181818181818181818181818181818181818181812121212121212121212121212121818181818181818181818183333313311121121112112333333331113311311311111311111111818181818182244442222222244424444444411111111111111111111111111111313131313131313222244444111111111111111111111111111111111111111111111311131313131313131313131322222123456789101112131415161718ug195_c3_02_031507Figure 3-4:FF324 Package—LX30 and LX50 SelectIO Bank Diagram

Virtex-5 FPGA Packaging and Pinout Specification

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